FIGURE 13. TRANSMITTER O
參數(shù)資料
型號： XR17V358IB176-F
廠商： Exar Corporation
文件頁數(shù)： 40/68頁
文件大?。?/td> 0K
描述： IC UART PCIE OCTAL 176FPBGA
產(chǎn)品培訓(xùn)模塊： PCIe UARTs
UART Product Overview
標(biāo)準(zhǔn)包裝： 160
特點(diǎn)： *
通道數(shù)： 1，UART
FIFO's： 256 字節(jié)
規(guī)程： RS485
電源電壓： 1.2V，3.3V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 176-LFBGA
供應(yīng)商設(shè)備封裝： 176-FPBGA（13x13）
包裝： 托盤
配用： 1016-1296-ND - EVAL BOARD FOR XR17V358-E8
1016-1295-ND - EVAL BOARD FOR XR17V358-E4
1016-1293-ND - EVAL BOARD FOR XR17V358
其它名稱： 1016-1294
FIGURE 13. TRANSMITTER OPERATION IN NON-FIFO MODE
Tr a n s m it
Ho ld in g
R egis t e r
( T HR)
T r an s m it S h if t R e gis t er ( T S R )
Da t a
By t e
L
S
B
M
S
B
T H R In te r r u p t ( IS R b it- 1 )
E nab led by I E R bit - 1
1 6X or 8X or 4X
Clo c k
XR17V358
45
REV. 1.0.4
HIGH PERFORMANCE OCTAL PCI EXPRESS UART
3.6.3
Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 256 bytes of transmit data. The THR empty flag (LSR bit [5]) is
set whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit [1])
when the amount of data in the FIFO falls below its programmed trigger level (see TXTRG register). The
transmit empty interrupt is enabled by IER bit [1]. The TSR flag (LSR bit [6]) is set when TSR becomes
completely empty. Furthermore, with the RS485 half-duplex direction control enabled (FCTR bit [5]=1) the
source of the transmit empty interrupt changes to TSR empty instead of THR empty. This is to ensure the
RTS# output is not changed until the last stop bit of the last character is shifted out.
3.6.4
Auto RS485 Operation
The auto RS485 half-duplex direction control changes the behavior of the transmitter when enabled by FCTR
bit [5]. It de-asserts RTS# or DTR# after a specified delay indicated in MSR[7:4] following the last stop bit of the
last character that has been transmitted. This helps in turning around the transceiver to receive the remote
station’s response. The delay optimizes the time needed for the last transmission to reach the farthest station
on a long cable network before switching off the line driver. This delay prevents undesirable line signal
disturbance that causes signal degradation. It also changes the transmitter empty interrupt to TSR empty
instead of THR empty.
FIGURE 14. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE
Transmit Data Shift Register
(TSR)
Transmit
Data Byte
THR Interrupt (ISR bit-1) falls
below Programmed Trigger
Level (TXTRG) and then
when becomes empty. FIFO
is Enabled by FCR bit-0=1
Transmit
FIFO
(256-Byte)
16X or 8X or 4X
Clock
Auto CTS Flow Control (CTS# pin)
Auto Software Flow Control
Flow Control Characters
(Xoff1/2 and Xon1/2 Reg.
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