參數(shù)資料
型號(hào)： XR17L152IM
廠商： EXAR CORP
元件分類： 微控制器/微處理器
英文描述： CAP .068UF 400V PEN FILM 2825 5%
中文描述： 2 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, PQFP100
封裝： 14 X 14 MM, 1 MM HEIGHT, TQFP-100
文件頁(yè)數(shù)： 9/55頁(yè)
文件大?。?/td> 318K
代理商： XR17L152IM
XR17L152
3.3V PCI BUS DUAL UART
REV. 1.1.0
á
DISCONTINUED
9
1.2
The device configuration registers and a special way to access each of the UART’s transmit and receive data
FIFOs are accessible directly from the PCI data bus. This provides easy programming of general operating
parameters to the L152 UART and for monitoring the status of various functions. The registers occupy 1K of
PCI bus memory address space. These addresses are offset onto the basic memory address, a value loaded
into the Memory Base Address Register (BAR) in the PCI local bus configuration register set. These registers
control or report on both channel UARTs functions that include interrupt control and status, 16-bit general
purpose timer control and status, multipurpose inputs/outputs control and status, sleep mode control, soft-
reset control, and device identification and revision, and others.
The registers set is mapped into 2 address blocks where each UART channel occupies 512 bytes memory
space for its own 16550 compatible configuration registers. The device configuration and control registers are
embedded inside the UART channel zero’s address space between 0x0080 to 0x0093. All these registers can
be accessed in 8, 16, 24 or 32 bit width depending on the starting address given by the host at beginning of the
bus cycle. Transmit and receive data may be loaded or unloaded in 8, 16, 24 or 32 bit format to the register’s
address. Every time a read or write operation is made to the transmit or receive register, its FIFO data pointer
is automatically bumped to the next sequential data location either in byte, word or dword. One special case
applies to the receive data unloading when reading the receive data together with its LSR register content. The
host must read them in 16 or 32 bits format in order to maintain integrity of the data byte with its associated
error tags.
Device configuration Register Set
0x34
31:0
RO
Reserved (returns zeros)
0x00000000
0x38
31:0
RO
Reserved (returns zeros)
0x00000000
0x3C
31:24
RO
Unimplemented MAXLAT
0x00
23:16
RO
Unimplemented MINGNT
0x00
15:8
RO
Interrupt Pin, use INTA#.
0x01
7:0
RWR
Interrupt Line.
0xXX
N
OTE
:
RWR
1
=Read/Write from external EEPROM. RWR=Read/Write from AD[31:0]. RO= Read Only. WO=Write Only.
T
ABLE
2: XR17L152 D
EVICE
C
ONFIGURATION
R
EGISTERS
O
FFSET
A
DDRESS
M
EMORY
S
PACE
R
EAD
/W
RITE
D
ATA
W
IDTH
C
OMMENT
0x000 - 0x00F
UART channel 0 Regs
(
Table 10
&
Table 11
)
8/16/24/32
First 8 regs are 16550 compatible
0x010 - 0x07F
Reserved
0x080 - 0x093
DEVICE CONFIG.
REGISTERS
(
Table 3
)
8/16/24/32
0x094 - 0x0FF
Reserved
Read/Write
0x100
UART 0 – Read FIFO
Read-Only
8/16/24/32
64 bytes of RX FIFO data
0x100
UART 0 – Write FIFO
Write-Only
8/16/24/32
64 bytes of TX FIFO data
0x140 - 0x17F
Reserved
0x180 - 0x1FF
UART 0 – Read FIFO
with status
Read-Only
16/32
64 bytes of RX FIFO data + LSR
T
ABLE
1: PCI L
OCAL
B
US
C
ONFIGURATION
S
PACE
R
EGISTERS
A
DDRESS
B
ITS
T
YPE
D
ESCRIPTION
R
ESET
V
ALUE
(
HEX
)
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