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參數(shù)資料
| 型號： | XR17L152IM |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CAP .068UF 400V PEN FILM 2825 5% |
| 中文描述： | 2 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1 MM HEIGHT, TQFP-100 |
| 文件頁數(shù)： | 8/55頁 |
| 文件大?。?/td> | 318K |
| 代理商： | XR17L152IM |
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DISCONTINUED
XR17L152
3.3V PCI BUS DUAL UART
REV. 1.1.0
8
0x04
31
30
29:28
RWC
RWC
RO
Parity error detected. Cleared by writing a logic 1.
System error detected. Cleared by writing a logic 1.
Unused
0000
27
R-Reset
Target Abort. Set whenever L152 terminates with a target abort.
0
26:25
RO
DEVSEL# timing.
00
24
RO
Unimplemented bus master error reporting bit
0
23
RO
Fast back to back transactions are supported
1
22:16
RO
Reserved Status bits
000 0000
15:9,7,
5,4,3,2
RO
Command bits (reserved)
0x0000
8
RWR
SERR# driver enable. Logic 1=enable driver and 0=disable driver
0
6
RWR
Parity error enable. Logic 1=respond to parity error and 0=ignore
0
1
RWR
Command controls a device’s response to mem space accesses:
0=disable mem space accesses, 1=enable mem space accesses
0
0
RO
Command controls a device’s response to I/O space accesses:
0 = disable I/O space accesses 1 = enable I/O space accesses
0
0x08
31:8
RO
Class Code (Simple 550 Communication Controller).
0x070002
7:0
RO
Revision ID (Exar device revision number)
0x01
0x0C
31:24
RO
BIST (Built-in Self Test)
0x00
23:16
RO
Header Type (a single function device with one BAR)
0x00
15:8
RO
Unimplemented Latency Timer (needed only for bus master)
0x00
7:0
RO
Unimplemented Cache Line Size
0x00
0x10
31:10
RWR
Memory Base Address Register (BAR)
0x00 00 00
9:0
RO
Claims a 1K address space for the memory mapped UARTs
00 0000 0000
0x14
31:0
RO
Unimplemented Base Address Register (returns zeros)
0x00000000
0x18h
31:0
RO
Unimplemented Base Address Register (returns zeros)
0x00000000
0x1C
31:0
RO
Unimplemented Base Address Register (returns zeros)
0x00000000
0x20
31:0
RO
Unimplemented Base Address Register (returns zeros)
0x00000000
0x24
31:0
RO
Unimplemented Base Address Register (returns zeros)
0x00000000
0x28
31:0
RO
Reserved
0x00000000
0x2C
31:16
RWR
1
Subsystem ID (write
from external EEPROM by customer)
0x0000
15:0
RWR
1
Subsystem Vendor ID (write
from external EEPROM by cus-
tomer)
0x0000
0x30
31:0
RO
Expansion ROM Base Address (Unimplemented)
0x00000000
T
ABLE
1: PCI L
OCAL
B
US
C
ONFIGURATION
S
PACE
R
EGISTERS
A
DDRESS
B
ITS
T
YPE
D
ESCRIPTION
R
ESET
V
ALUE
(
HEX
)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR17L154 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V PCI BUS QUAD UART |
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| XR17L154IV | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V PCI BUS QUAD UART |
| XR17V252 | 制造商:EXAR 制造商全稱:EXAR 功能描述:66 MHZ PCI BUS DUAL UART WITH POWER MANAGEMENT SUPPORT |
| XR17V252_08 | 制造商:EXAR 制造商全稱:EXAR 功能描述:66 MHZ PCI BUS DUAL UART WITH POWER MANAGEMENT SUPPORT |
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