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參數(shù)資料
| 型號(hào)： | XR17L152IM |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CAP .068UF 400V PEN FILM 2825 5% |
| 中文描述： | 2 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1 MM HEIGHT, TQFP-100 |
| 文件頁數(shù)： | 40/55頁 |
| 文件大?。?/td> | 318K |
| 代理商： | XR17L152IM |
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DISCONTINUED
XR17L152
3.3V PCI BUS DUAL UART
REV. 1.1.0
40
MSR[7]: CD Input Status
CD# (active high, logical 1). Normally this bit is the compliment of the CD# input. In the loopback mode this bit
is equivalent to bit-3 in the MCR register. The CD# input may be used as a general purpose input
when the modem interface is not used.
Modem Status Register (MSR) - Write Only
The upper four bits 4-7 of this register sets the delay in number of bits time for the auto RS485 turn around from
transmit to receive.
MSR [7:4]
When Auto RS485 feature is enabled (FCTR bit-5=1) and RTS# output is connected to the enable input of a
RS-485 transceiver. These 4 bits select from 0 to 15 bit-time delay after the end of the last stop-bit of the last
transmitted character. This delay controls when to change the state of RTS# output. This delay is very useful in
long-cable networks.
Table 15
shows the selection. The bits are enabled by EFR bit-4.
Scratch Pad Register (SPR)
This is an 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
Feature Control Register (FCTR)
This register controls the UART enhanced functions that are not available on ST16C554 or ST16C654.
T
ABLE
15: A
UTO
RS485 H
ALF
-
DUPLEX
D
IRECTION
C
ONTROL
D
ELAY
FROM
T
RANSMIT
-
TO
-R
ECEIVE
MSR[7]
MSR[6]
MSR[5]
MSR[4]
D
ELAY
IN
D
ATA
B
IT
(
S
) T
IME
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
9
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
0
0
0
8
1
0
0
1
9
1
0
1
0
10
1
0
1
1
11
1
1
0
0
12
1
1
0
1
13
1
1
1
0
14
1
1
1
1
15
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| XR17L152 | 3.3V PCI BUS DUAL UART |
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