參數(shù)資料
型號(hào): XR17D154
廠商: Exar Corporation
英文描述: UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
中文描述: 通用(3.3V和5V)PCI總線四的UART
文件頁(yè)數(shù): 10/69頁(yè)
文件大?。?/td> 836K
代理商: XR17D154
XR17D154
xr
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
REV. 1.2.0
18
TIMER [15:8] - Reserved
TIMERMSB [31:24] and TIMERLSB [23:16]
TIMERMSB and TIMERLSB form a 16-bit value. The least-significant bit of the timer is being bit [0] of the
TIMERLSB with most-significant-bit being bit [7] in TIMERMSB. Notice that these registers do not hold the
current counter value when read. Reading the TIMERCNTL register will clear its interrupt. Default value is
zero (timer disabled) upon powerup and reset.
2.2.3
8XMODE [7:0] - (default 0x00)
Each bit selects 8X or 16X sampling rate for that UART channel, bit-0 is channel 0. Logic 0 (default) selects
normal 16X sampling with logic one selects 8X sampling rate. Transmit and receive data rates will double by
selecting 8X.
2.2.4
REGA [15:8] Reserved
2.2.5
RESET [23:16] - (default 0x00)
The 8-bit Reset register [RESET] provides the software with the ability to reset the UART(s) when there is a
need. Each bit is self-resetting after it is written a logic 1 to perform a reset to that channel. All registers in that
channel will be reset to the default condition, see Table 20 on page 51 for details. Bit-0 =1 resets UART
channel 0 with bit-3=1 resets channel 3..
T IM E RCNT L Reg ister
Rs vd
M P IO [0 ]
C ontro l
Clo c k
Se le c t
S ingle /
R e -trig g e r
Sta rt/
Sto p
IN T
E n able
B it-7 B it-6
B it-5
B it-4
B it-3
B it-2
B it-1
B it-0
TIM E R M S B R eg ister
B it-1 5
B it-1 4
B it-1 3
B it-1 2
B it-1 1
B it-1 0
B it-9
B it-8
TIM E R L S B R eg ister
B it-7
B it-6
B it-5
B it-4
B it-3
B it-2
B it-1 B it-0
1 6 -B it T im e r/C o u n te r P ro g ra m m a b le R e g is te rs
Rsvd
Rsvd Rsvd Ch-3 Ch-2 Ch-1 Ch-0
8X M O DE Register
Individual U A R T C hannel 8X C lock M ode E nable
B it-7 B it-6
B it-5
B it-4
B it-3
B it-2
B it-1 B it-0
Rsvd
Rsvd Rsvd Ch-3 Ch-2 Ch-1 Ch-0
RES ET Register
Individual U A R T C hannel R eset E nable
B it-7 B it-6 B it-5 B it-4 B it-3
B it-2
B it-1
B it-0
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