XR16M564/564D
4
1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO
REV. 1.0.0
PIN DESCRIPTIONS
ORDERING INFORMATION
PART NUMBER
PACKAGE
OPERATING TEMPERATURE
RANGE
DEVICE STATUS
XR16M564IJ68
68-Lead PLCC
-40°C to +85°C
Active
XR16M564IV64
64-Lead LQFP
-40°C to +85°C
Active
XR16M564DIV64
64-Lead LQFP
-40°C to +85°C
Active
XR16M564IL48
48-pin QFN
-40°C to +85°C
Active
XR16M564IV80
80-Lead LQFP
-40°C to +85°C
Active
Pin Description
NAME
48-QFN
PIN #
64-LQFP
PIN #
68-PLCC
PIN #
80-LQFP
PIN #
TYPE
DESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
15
16
17
22
23
24
32
33
34
46
47
48
I
Address data lines [2:0]. These 3 address lines select
one of the internal registers in UART channel A-D dur-
ing a data bus transaction.
D7
D6
D5
D4
D3
D2
D1
D0
46
45
44
43
42
41
40
39
60
59
58
57
56
55
54
53
5
4
3
2
1
68
67
66
15
14
13
12
11
9
8
I/O
Data bus lines [7:0] (bidirectional).
IOR#
(VCC)
29
40
52
70
I
When 16/68# pin is HIGH, the Intel bus interface is
selected and this input becomes read strobe (active
low). The falling edge instigates an internal read cycle
and retrieves the data byte from an internal register
pointed by the address lines [A2:A0], puts the data
byte on the data bus to allow the host processor to
read it on the rising edge.
When 16/68# pin is LOW, the Motorola bus interface is
selected and this input is not used and should be con-
nected to VCC.
IOW#
(R/W#)
7
9
18
31
I
When 16/68# pin is HIGH, it selects Intel bus interface
and this input becomes write strobe (active low). The
falling edge instigates the internal write cycle and the
rising edge transfers the data byte on the data bus to
an internal register pointed by the address lines.
When 16/68# pin is LOW, the Motorola bus interface is
selected and this input becomes read (logic 1) and
write (LOW) signal.
CSA#
(CS#)
5
7
16
28
I
When 16/68# pin is HIGH, this input is chip select A
(active low) to enable channel A in the device.
When 16/68# pin is LOW, this input becomes the chip
select (active low) for the Motorola bus interface.