REV. 1.0.2 2.12 Auto RTS (Hardware) Flow Cont" />
參數(shù)資料
型號: XR16M2551IL32TR-F
廠商: Exar Corporation
文件頁數(shù): 8/51頁
文件大?。?/td> 0K
描述: IC UART FIFO 16B DUAL 32QFN
標準包裝: 3,000
特點: *
通道數(shù): 2,DUART
FIFO's: 16 字節(jié)
規(guī)程: RS232,RS422
電源電壓: 1.62 V ~ 3.63 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應商設備封裝: 32-QFN 裸露焊盤(5x5)
包裝: 帶卷 (TR)
XR16M2551
16
HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE
REV. 1.0.2
2.12
Auto RTS (Hardware) Flow Control
Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#
output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control
features is enabled to fit specific application requirement (see Figure 10):
Enable auto RTS flow control using EFR bit-6.
The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to HIGH after it is enabled).
If using the Auto RTS interrupt:
Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the
RTS# pin makes a transition from low to high: ISR bit-5 will be set to HIGH.
FIGURE 9. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
Receive Data Shift
Register (RSR)
RXFIFO1
16X or 8X or 4X Clock
( DLD[5:4] )
Er
ror
T
ags
(16
-s
et
s)
E
rro
rT
ag
s
in
LS
R
b
its
4:2
Receive Data Characters
FIFO
Trigger=8
Example
: - RX FIFO trigger level selected at 8 bytes
(See Note Below)
Data fills to
14
Data falls to
4
Data Bit
Validation
Receive
Data FIFO
Receive
Data
Receive Data
Byte and Errors
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
16 bytes by 11-bit wide
FIFO
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