XR16M2551
8
HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE
REV. 1.0.2
2.0 FUNCTIONAL DESCRIPTIONS
2.1
CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The M2551 data interface supports the Intel compatible types of CPUs and it is compatible
to the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data
bus transaction. Each bus cycle is asynchronous using CSA#/CSB#, IOR# and IOW# or CS#, R/W# and A3
inputs. Both UART channels share the same data bus for host operations. A typical data bus interconnection
for Intel and Motorola mode is shown in Figure 3.
2.2
Device Reset
The RESET input resets the internal registers and the serial interface outputs in both channels to their default
state (see Table 16). An active high pulse of longer than 40 ns duration will be required to activate the reset
function in the device.
FIGURE 3. XR16M2551 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS
VCC
OP2A#
DSRA#
CTSA#
RTSA#
DTRA#
RXA
TXA
RIA#
CDA#
OP2B#
DSRB#
CTSB#
RTSB#
DTRB#
RXB
TXB
RIB#
CDB#
GND
A0
A1
A2
UART_CSA#
UART_CSB#
IOR#
IOW #
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
CSA#
CSB#
D0
D1
D2
D3
D4
D5
D6
D7
IOR#
IOW #
UART
Channel A
UART
Channel B
UART_INTB
UART_INTA
INTB
INTA
RXRDYA#
TXRDYA#
RXRDYA#
TXRDYA#
RXRDYB#
TXRDYB#
RXRDYB#
TXRDYB#
UART_RESET
RESET
Serial Interface of
RS-232, RS-422
Serial Interface of
RS-232, RS-422
(no connect)
1.62 to 3.63 Volt VCC
VCC
OP2A#
DSRA#
CTSA#
RTSA#
DTRA#
RXA
TXA
RIA#
CDA#
OP2B#
DSRB#
CTSB#
RTSB#
DTRB#
RXB
TXB
RIB#
CDB#
GND
A0
A1
A2
UART_CS#
A3
R/W #
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
CSA#
CSB#
D0
D1
D2
D3
D4
D5
D6
D7
IOR#
IOW #
UART
Channel A
UART
Channel B
UART_IRQ#
INTB
INTA
RXRDYA#
TXRDYA#
RXRDYA#
TXRDYA#
RXRDYB#
TXRDYB#
RXRDYB#
TXRDYB#
RESET#
VCC
UART_RESET#
(no connect)
VCC
Intel Data Bus Interconnections
Motorola Data Bus Interconnections
Serial Interface of
RS-232, RS-422
Serial Interface of
RS-232, RS-422