REV. 1.4.2 2.12 Auto RTS (Hardware) Flow Control This " />
參數資料
型號: XR16L580IMTR-F
廠商: Exar Corporation
文件頁數: 8/49頁
文件大小: 0K
描述: IC UART FIFO 16B 48TQFP
標準包裝: 1,500
特點: *
通道數: 1,UART
FIFO's: 16 字節(jié)
規(guī)程: RS232,RS422
電源電壓: 2.25 V ~ 5.5 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調制解調器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP
供應商設備封裝: 48-TQFP(7x7)
包裝: 帶卷 (TR)
XR16L580
16
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
REV. 1.4.2
2.12
Auto RTS (Hardware) Flow Control
This feature is not available in the 24-QFN package since it does not have the RTS# pin.
Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#
output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control
features is enabled to fit specific application requirement (see
Enable auto RTS flow control using EFR bit-6.
The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled).
If using the Auto RTS interrupt:
Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the
RTS# pin makes a transition from low to high: ISR bit-5 will be set to logic 1.
2.13
Auto RTS Hysteresis
The L580 has a new feature that provides flow control trigger hysteresis while maintaining compatibility with
the ST16C550 UART. With the Auto RTS function enabled, an interrupt is generated when the receive FIFO
reaches the programmed RX trigger level. The RTS# pin will not be forced to a logic 1 (RTS off), until the
receive FIFO reaches one trigger level above the programmed trigger level in the trigger table (
Table 8). The
RTS# pin will return to a logic 0 after the RX FIFO is unloaded to one trigger level lower than the programmed
trigger level. This is described in
Figure 11. Under the above described conditions, the L580 will continue to
accept data until the receive FIFO gets full. The Auto RTS function is initiated when the RTS# output pin is
asserted to a logic 0 (RTS On).
2.14
Auto CTS Flow Control
This feature is not available in the 24-QFN package since it does not have the CTS# pin.
Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is
monitored to suspend/restart the local transmitter. The auto CTS flow control feature is selected to fit specific
application requirement (see
Enable auto CTS flow control using EFR bit-7.
If using the Auto CTS interrupt:
Enable CTS interrupt through IER bit-7 (after setting EFR bit-4). The UART issues an interrupt when the
CTS# pin is de-asserted (HIGH): ISR bit-5 will be set to 1, and UART will suspend transmission as soon as
the stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input is re-
asserted (LOW), indicating more data may be sent.
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