XR16L580
35
REV. 1.4.2
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
EFR[6]: Auto RTS Flow Control Enable
This bit has no functionality in the 24-QFN package.
RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is
selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and
RTS de-asserts to a logic 1 at one trigger level above the programmed trigger level. RTS# will return to a logic
0 when FIFO data falls below one trigger level below the programmed trigger level. The RTS# output must be
asserted (logic 0) before the auto RTS can take effect. RTS# pin will function as a general purpose output
when hardware flow control is disabled.
Logic 0 = Automatic RTS flow control is disabled (default).
Logic 1 = Enable Automatic RTS flow control.
EFR[7]: Auto CTS Flow Control Enable
This bit has no functionality in the 24-QFN package.
Automatic CTS Flow Control.
Logic 0 = Automatic CTS flow control is disabled (default).
Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts to logic
1. Data transmission resumes when CTS# returns to a logic 0.
4.16
Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Write Only
These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2.
For more details, refer to