REV. 2.3.1 2.97V TO 5.5V UART WITH 128-BYTE FIFO 9 2.0 FUNCTIONAL DESCRIPTIONS 2.1 Host Data Bus Interface The host i" />
參數(shù)資料
型號(hào): XR16C850CMTR-F
廠商: Exar Corporation
文件頁數(shù): 56/56頁
文件大?。?/td> 0K
描述: IC UART FIFO 128B 48TQFP
標(biāo)準(zhǔn)包裝: 1,500
特點(diǎn): *
通道數(shù): 1,UART
FIFO's: 128 字節(jié)
規(guī)程: RS485
電源電壓: 2.97 V ~ 5.5 V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 帶卷 (TR)
xr
XR16C850
REV. 2.3.1
2.97V TO 5.5V UART WITH 128-BYTE FIFO
9
2.0 FUNCTIONAL DESCRIPTIONS
2.1
Host Data Bus Interface
The host interface is 8 data bits wide with 3 address lines and control signals to execute bus read and write
transactions. The 850 supports 2 types of host interfaces: Intel and PC mode. The Intel bus interface is
selected by connecting SEL to logic 1. When the SEL pin is set to a logic 1, the 850 interface is the same as
industry standard 16C550. The Intel bus interconnections are shown in Figure 3. The special PC mode is
selected when SEL is connected to logic 0. The PC mode interconnections are shown in Figure 4.
.
FIGURE 3. XR16C850 INTEL BUS INTERCONNECTIONS
FIGURE 4. XR16C850 PC MODE INTERCONNECTIONS
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IOR
IOW
RESET
D0
D1
D2
D3
D4
D5
D6
D7
IOR#
IOW #
A0
A1
A2
CS2#
RESET
VCC
CS0
CS1
AS#
IOR
IOW
INT
RCLK
BAUDOUT#
SEL
VCC
GND
CS#
OP2#
OP1#
DSR#
CTS#
RTS#
DTR#
RX
TX
RI#
CD#
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7
A14
A15
AEN#
IOW#
IOR#
RESET
D0
D1
D2
D3
D4
D5
D6
D7
IOW#
A0
A1
A2
RESET
VCC
IRQn
IRQA
SEL
VCC
GND
IOR#
IRQB
IRQC
IRQ4
IRQ3
A3
A4
A5
A6
A7
A8
A9
AEN
OP1#
RI#
CD#
DSR#
CTS#
RX
TX
RTS#
DTR#
S1
S2
S3
VCC
GND
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