REV. 2.3.1 44 TRD2 Delay from Chip Select to I" />
參數(shù)資料
型號: XR16C850CMTR-F
廠商: Exar Corporation
文件頁數(shù): 39/56頁
文件大?。?/td> 0K
描述: IC UART FIFO 128B 48TQFP
標(biāo)準(zhǔn)包裝: 1,500
特點: *
通道數(shù): 1,UART
FIFO's: 128 字節(jié)
規(guī)程: RS485
電源電壓: 2.97 V ~ 5.5 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 帶卷 (TR)
XR16C850
xr
2.97V TO 5.5V UART WITH 128-BYTE FIFO
REV. 2.3.1
44
TRD2
Delay from Chip Select to IOR#
10
5
ns
TDIS
Delay from IOR# to DDIS#
20
10
ns
TWR1
Delay from AS# to IOW#
10
5
ns
TDS2
Data Setup Time (AS# used)
20
15
ns
TDH2
Data Hold Time (AS# used)
5
ns
TAS3
Address Setup Time (PC Mode)
10
5
ns
TRD3
Delay from AEN# to IOR#
10
5
ns
TRD4
Delay from IOR# to AEN#
10
5
ns
TWR2
Delay from AEN# to IOW#
10
5
ns
TWR3
Delay from IOW# to AEN#
5
ns
TDS3
Data Setup Time (PC Mode)
20
15
ns
TDH3
Data Hold Time (PC Mode)
5
ns
TWDO
Delay From IOW# To Output
75
50
ns
TMOD
Delay To Set Interrupt From MODEM Input
75
50
ns
TRSI
Delay To Reset Interrupt From IOR#
75
50
ns
TSSI
Delay From Stop To Set Interrupt
1
Bclk
TRRI
Delay From IOR# To Reset Interrupt
75
50
ns
TSI
Delay From Stop To Interrupt
75
50
ns
TINT
Delay From Initial INT Reset To Transmit Start
8
24
8
24
Bclk
TWRI
Delay From IOW# To Reset Interrupt
75
50
ns
TSSR
Delay From Stop To Set RXRDY#
1
Bclk
TRR
Delay From IOR# To Reset RXRDY#
75
50
ns
TWT
Delay From IOW# To Set TXRDY#
75
50
ns
TSRT
Delay From Center of Start To Reset TXRDY#
8
Bclk
TRST
Reset Pulse Width
40
ns
N
Baud Rate Divisor
1
216-1
1
216-1
-
Bclk
Baud Clock
16X
Hz
AC ELECTRICAL CHARACTERISTICS
TA=0O TO 70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.97V TO 5.5V, 70 PF LOAD WHERE
APPLICABLE
SYMBOL
PARAMETER
LIMITS
3.3V
MIN
MAX
LIMITS
5.0V
MIN
MAX
UNIT
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