REV. 2.3.1 2.97V TO 5.5V UART WITH 128-BYTE FIFO 51 FIGURE 29. T
參數(shù)資料
型號: XR16C850CMTR-F
廠商: Exar Corporation
文件頁數(shù): 47/56頁
文件大?。?/td> 0K
描述: IC UART FIFO 128B 48TQFP
標準包裝: 1,500
特點: *
通道數(shù): 1,UART
FIFO's: 128 字節(jié)
規(guī)程: RS485
電源電壓: 2.97 V ~ 5.5 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調制解調器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP
供應商設備封裝: 48-TQFP(7x7)
包裝: 帶卷 (TR)
xr
XR16C850
REV. 2.3.1
2.97V TO 5.5V UART WITH 128-BYTE FIFO
51
FIGURE 29. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED]
FIGURE 30. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED]
TX
TXRDY#
IOW#
INT*
TXDMA#
D0:D7
S
D0:D7
T
D0:D7
S
D0:D7
S
T
D0:D7
S
T
D0:D7
S
T
Start
Bit
Stop
Bit
T
WRI
(Unloading)
(Loading data
into FIFO)
Last Data Byte
Transmitted
TX FIFO fills up
to trigger level
TX FIFO drops
below trigger level
Data in
TX FIFO
Empty
T
WT
T
SRT
TX FIFO
Empty
T
S
T
SI
ISR is read
IER[1]
enabled
ISR is read
*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.
TX
TXRDY#
IOW#
INT*
D0:D7
S
TXDMA
D0:D7
S
D0:D7
T
D0:D7
S
D0:D7
S
T
D0:D7
S
T
D0:D7
S
T
Start
Bit
Stop
Bit
T
WRI
T
(Unloading)
(Loading data
into FIFO)
Last Data Byte
Transmitted
TX FIFO fills up
to trigger level
TX FIFO drops
below trigger level
At least 1
empty location
in FIFO
T
SRT
TX FIFO
Full
T
WT
T
SI
ISR Read
*INT cleared when the ISR is read or when TX FIFO fills up to trigger level.
IER[1]
enabled
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