參數(shù)資料
型號(hào): XR-215A
廠商: Exar Corporation
英文描述: Monolithic Phase Locked Loop
中文描述: 單片鎖相環(huán)
文件頁數(shù): 17/32頁
文件大?。?/td> 331K
代理商: XR-215A
XR-215A
17
Rev. 1.01
Figure 14. Linearized Model of a PLL as a
Negative Feedback System
F(s)
K
d
0
s
Ko
s
-
Phase Comparator Gain K
d
The output voltage from the phase comparator per radian
of phase difference at the phase comparator inputs (pins
4 and 6). The units are volts/radians. (See Figure 9.)
VCO Conversion Gain Ko
The VCO voltage-to-frequency conversion gain is
determined by the choice of timing capacitor C
0
and gain
control resistor, R
0
connected externally across pins 11
and 12. It can be expressed as:
700
C
0
R
0
K
0
(radians/sec/volt)
where C
0
is in F and R
0
is in k . For most applications,
recommended values for R
0
range from 1k to 10k .
Lock Range ( wL)
The range of frequencies in the vicinity of f
o
, over which
the PLL can maintain lock with an input signal. It is also
known as the “tracking” or “holding” range. If saturation or
limiting does not occur, the lock range is equal to the loop
gain, i.e.
L
= K
T
= K
d
K
o
.
Capture Range ( wC)
The band of frequencies in the vicinity of f
o
where the PLL
can establish or acquire lock with an input signal. It is also
known as the “acquisition” range. It is always smaller than
the lock range and is related to the low-pass filter
bandwidth. It can be approximated by a parametric
equation of the form:
C
L
|F(j
C
)|
where |F(j
at =
C
| is the low-pass filter magnitude response
C
. For a simple lag filter, it can be expressed as:
L
T
1
C
where T
1
is the filter time constant.
Amplifier Gain AV
The voltage gain of the amplifier section is determined by
feedback resistors R
F
and Rp between pins (8,1) and
(2,1) respectively. (See Figure 3 and Figure 4.) It is given
by:
–R
F
R
1
R
P
A
V
where R
1
is the (6k ) internal impedance at pin 2.
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