參數(shù)資料
型號: XPC855TZP80
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù): 3/76頁
文件大?。?/td> 825K
代理商: XPC855TZP80
MOTOROLA
MPC850 (Rev. A/B/C) Hardware Specifications
3
Part II Features
Figure 2-1 is a block diagram of the MPC850, showing its major components and the
relationships among those components:
Figure 2-1. MPC850 Microprocessor Block Diagram
The following list summarizes the main features of the MPC850:
Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC
architecture) with thirty-two 32-bit general-purpose registers (GPRs)
— Performs branch folding and branch prediction with conditional prefetch, but
without conditional execution
System Interface Unit
Memory Controller
Bus Interface Unit
System Functions
Real-Time Clock
PCMCIA Interface
Bus
Embedded
MPC8xx
Core
2-Kbyte
I-Cache
MMU
1-Kbyte
D-Cache
Data
MMU
Load/Store
Instruction
Bus
Parallel I/O
Ports
Baud Rate
Generators
Dual-Port
RAM
Interrupt
Controller
Four
Timers
20 Virtual
Serial DMA
2 Virtual
IDMA
Channels
32-Bit RISC Communications
Processor (CP) and Program ROM
SCC2
USB
SPI
Timer
Non-Multiplexed Serial Interface
Instruction
Channels
and
Unified Bus
Communications
Processor
Module
Peripheral Bus
SCC3
I
2
C
UTOPIA
(850SR & DSL)
SMC1
SMC2
Time Slot Assigner
TDMa
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