參數(shù)資料
型號(hào): XIO2200AZHH
廠(chǎng)商: Texas Instruments
文件頁(yè)數(shù): 124/202頁(yè)
文件大?。?/td> 0K
描述: IC PCI-EXPRESS/BUS BRIDGE 175BGA
產(chǎn)品培訓(xùn)模塊: PCI Express Basics
標(biāo)準(zhǔn)包裝: 160
應(yīng)用: PCI Express 至 PCI 轉(zhuǎn)換橋
接口: PCI
電源電壓: 1.35 V ~ 1.65 V,3 V ~ 3.6 V
封裝/外殼: 175-BGA Microstar+
供應(yīng)商設(shè)備封裝: 175-BGA MICROSTAR(12x12)
包裝: 托盤(pán)
安裝類(lèi)型: 表面貼裝
產(chǎn)品目錄頁(yè)面: 882 (CN2011-ZH PDF)
配用: XIO2200AEVM-ND - XIO2200AEVM
其它名稱(chēng): 296-21636
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Introduction
15
March 5 2007 June 2011
SCPS154C
Table 29. 1394 Terminals
SIGNAL
GGW/
ZGW
BALL #
ZHH
BALL #
I/O
TYPE
CELL
TYPE
EXTERNAL
PARTS
DESCRIPTION
CNA
U09
N06
I/O
LV
CMOS
Cable not active. This terminal is asserted high when there are
no ports receiving incoming bias voltage. If it is not used, then
this terminal must be strapped to GND through a resistor.
CPS
T10
L07
I
Feed
through
External resistor
per 1394a
specification
Cable power status input. This terminal is normally connected to
cable power through a 400-kΩ resistor. This circuit drives an
internal comparator that detects the presence of cable power. If
CPS is not used to detect cable power, then this terminal must be
connected to VSSA.
PC0
PC1
PC2
U10
T09
R09
N07
M07
P07
I
LV
CMOS
External resistor
per 1394a
specification
Power class programming inputs. On hardware reset, these
inputs set the default value of the power class indicated during
self-ID. Programming is done by tying these terminals high or
low.
R0_1394
R1_1394
T17
R16
P14
N14
I/O
Bias
External resistor
per 1394a
specification
Current-setting resistor terminals. These terminals are connected
to an external resistance to set the internal operating currents
and cable driver output currents. A resistance of 6.34 kΩ ±1% is
required to meet the IEEE Std 1394-1995 output voltage limits.
TPA0P
TPA0N
T12
U12
P09
N09
I/O
LV
CMOS
External resistors
and capacitors
Twisted-pair cable A differential signal terminals. Board trace
lengths from each pair of positive and negative differential signal
pins must be matched and as short as possible to the external
TPA1P
TPA1N
T15
U15
P11
N11
I/O
LV
CMOS
and capacitors
per 1394a
specification
pins must be matched and as short as possible to the external
load resistors and to the cable connector. For an unused port,
TPA+ and TPA– can be left open.
TPBIAS0
TPBIAS1
U13
U16
L10
P12
O
Bias
External resistors
and capacitors
per 1394a
specification
Twisted-pair bias output. This provides the 1.86-V nominal bias
voltage needed for proper operation of the twisted-pair cable
drivers and receivers and for signaling to the remote nodes that
there is an active cable connection. Each of these pins must be
decoupled with a 1.0-μF capacitor to ground.
TPB0P
TPB0N
T11
U11
P08
N08
I/O
LV
CMOS
External resistors
and capacitors
Twisted-pair cable B differential signal terminals. Board trace
lengths from each pair of positive and negative differential signal
pins must be matched and as short as possible to the external
TPB1P
TPB1N
T14
U14
P10
N10
I/O
LV
CMOS
and capacitors
per 1394a
specification
pins must be matched and as short as possible to the external
load resistors and to the cable connector. For an unused port,
TPB+ and TPB– can be left open.
XI
XO
P17
P16
M14
M13
I
Feed
through
Crystal oscillator
per 1394a
specification
Crystal oscillator inputs. These terminals connect to a
24.576-MHz parallel resonant fundamental mode crystal. When
an external clock source is used, XI must be the input and XO
must be left open. The clock must be supplied before the device
is taken out of reset.
Table 210. Reserved Terminals
SIGNAL
GGW/ZGW BALL #
ZHH BALL #
I/O
TYPE
DESCRIPTION
RSVD
A02, A03, A05, A06,
A07, A08, A09, A10,
A11, A12, A13, A14,
B01, B03, B04, B05,
B06, B07, B09, B10,
B14, C01, C02, C04,
C07, C08, C11, C12,
D01, D02, D07, E02,
H01, H02, H03, J02,
J03, K01, K02, K03,
L01, L02, L03, L04,
M01, M02, N01, N02,
N15, N16, P01, P02,
R08, T08, U03, U04
A02, A03, A05, A06,
A07, A09, A13, B01,
B02, B03, B04, B05,
B06, B08, B09, B10,
B11, C01, C02, C03,
C04, C05, C06, C07,
C08, C09, C10, C11,
D02, D06, D07, D10,
D11, F02, F03, G02,
G03, H01, H02, H03,
H04, J01, J02, J03,
J04, K01, K02, K03,
L01, L02, L04, L14,
M06, M12, P01, P02,
P06
O
Reserved, do not connect to external signals.
Not Recommended for New Designs
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