參數(shù)資料
型號(hào): XIO2200AGGW
廠商: Texas Instruments
文件頁(yè)數(shù): 97/202頁(yè)
文件大小: 0K
描述: IC PCI-EXPRESS/BUS BRIDGE 176BGA
產(chǎn)品培訓(xùn)模塊: PCI Express Basics
標(biāo)準(zhǔn)包裝: 126
應(yīng)用: PCI Express 至 PCI 轉(zhuǎn)換橋
接口: PCI
電源電壓: 1.35 V ~ 1.65 V,3 V ~ 3.6 V
封裝/外殼: 176-LFBGA
供應(yīng)商設(shè)備封裝: 176-BGA MICROSTAR(15x15)
包裝: 托盤
安裝類型: 表面貼裝
產(chǎn)品目錄頁(yè)面: 882 (CN2011-ZH PDF)
配用: XIO2200AEVM-ND - XIO2200AEVM
其它名稱: 296-19617
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1394 PHY Configuration Space
173
March 5 2007 June 2011
SCPS154C
10.2 Port Status Register
The port status page provides access to configuration and status information for each of the ports. The port
is selected by writing 0 to the Page_Select field and the desired port number to the Port_Select field in base
register 7. Table 103 shows the configuration of the port status page registers and Table 104 shows the
corresponding field descriptions. If the selected port is not implemented, then all registers in the port status
page are read as 0.
Table 103. Page 0 (Port Status) Register Configuration
BIT POSITION
ADDRESS
0
1
2
3
4
5
6
7
1000
AStat
BStat
Ch
Con
Bias
Dis
1001
Peer_Speed
Int_enable
Fault
Reserved
1010
Reserved
1011
Reserved
1100
Reserved
1101
Reserved
1110
Reserved
1111
Reserved
Table 104. Page 0 (Port Status) Register Field Descriptions
FIELD
SIZE
TYPE
DESCRIPTION
AStat
2
R
TPA line state. This field indicates the TPA line state of the selected port, encoded as follows:
Code
Arb Value
11
Z
10
0
01
1
00
invalid
BStat
2
R
TPB line state. This field indicates the TPB line state of the selected port. This field has the same encoding as
the AStat field.
Ch
1
R
Child/parent status. A 1b indicates that the selected port is a child port. A 0b indicates that the selected port is
the parent port. A disconnected, disabled, or suspended port is reported as a child port. The Ch bit is invalid
after a bus reset until tree-ID has completed.
Con
1
R
Debounced port connection status. This bit indicates that the selected port is connected. The connection
must be stable for the debounce time of approximately 341 ms for the Con bit to be set to 1b. The Con bit is
cleared to 0b by system (hardware) reset and is unaffected by bus reset.
Note: The Con bit indicates that the port is physically connected to a peer PHY device, but the port is not
necessarily active.
Bias
1
R
Debounced incoming cable bias status. A 1b indicates that the selected port is detecting incoming cable
bias. The incoming cable bias must be stable for the debounce time of 52 μs for the Bias bit to be set to 1b.
Dis
1
RW
Port disabled control. If the Dis bit is set to 1b, then the selected port is disabled. The Dis bit is cleared to 0b by
system (hardware) reset (all ports are enabled for normal operation following system (hardware) reset). The
Dis bit is not affected by bus reset.
Peer_Speed
3
R
Port peer speed. This field indicates the highest speed capability of the peer PHY device connected to the
selected port, encoded as follows:
Code
Peer Speed
000
S100
001
S200
010
S400
011111
invalid
The Peer_Speed field is invalid after a bus reset until self-ID has completed.
Note: Peer speed codes higher than 010b (S400) are defined in IEEE Std 1394a-2000. However, the
controller is only capable of detecting peer speeds up to S400.
Not Recommended for New Designs
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