參數資料
| 型號： | XIO2200AGGW |
| 廠商： | Texas Instruments |
| 文件頁數： | 63/202頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-EXPRESS/BUS BRIDGE 176BGA |
| 產品培訓模塊： | PCI Express Basics |
| 標準包裝： | 126 |
| 應用： | PCI Express 至 PCI 轉換橋 |
| 接口： | PCI |
| 電源電壓： | 1.35 V ~ 1.65 V，3 V ~ 3.6 V |
| 封裝/外殼： | 176-LFBGA |
| 供應商設備封裝： | 176-BGA MICROSTAR（15x15） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
| 產品目錄頁面： | 882 (CN2011-ZH PDF) |
| 配用： | XIO2200AEVM-ND - XIO2200AEVM |
| 其它名稱： | 296-19617 |
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1394 OHCI Memory-Mapped Register Space
142
March 5 2007 June 2011
SCPS154C
8.21 Interrupt Event Register
The interrupt event set/clear register reflects the state of the various interrupt sources. The interrupt bits are
set to 1b by an asserting edge of the corresponding interrupt signal or by writing a 1b in the corresponding
bit in the set register. The only mechanism to clear a bit in this register is to write a 1b to the corresponding
bit in the clear register.
This register is fully compliant with the 1394 Open Host Controller Interface Specification, and the controller
adds a vendor-specific interrupt function to bit 30. When the interrupt event register is read, the return value
is the bit-wise AND function of the interrupt event and interrupt mask registers. See Table 815 for a complete
description of the register contents.
OHCI register offset:
80h set register
84h clear register [returns the content of the interrupt event register bit-wise
ANDed with the interrupt mask register when read]
Register type:
Read/Set/Clear/Update, Read/Set/Clear, Read/Update, Read-only
Default value:
XXXX 0XXXh
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
X
0
X
0
X
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
X
Table 815. Interrupt Event Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
3130
RSVD
R
Reserved. Bits 31 and 30 return 00b when read.
29
SoftInterrupt
RSC
Bit 29 is used by software to generate an interrupt for its own use.
28
RSVD
R
Reserved. Bit 28 returns 0b when read.
27
ack_tardy
RSCU
Bit 27 is set to 1b when bit 29 (AckTardyEnable) in the host controller control register at OHCI offset
50h/54h (see Section 8.16) is set to 1b and any of the following conditions occur:
a. Data is present in a receive FIFO that is to be delivered to the host.
b. The physical response unit is busy processing requests or sending responses.
c. The controller sent an ack_tardy acknowledgment.
26
phyRegRcvd
RSCU
The controller has received a PHY register data byte which can be read from bits 2316 in the PHY
layer control register at OHCI offset ECh (see Section 8.33).
25
cycleTooLong
RSCU
If bit 21 (cycleMaster) in the link control register at OHCI offset E0h/E4h (see Section 8.31) is set to
1b, then this indicates that over 125 μs has elapsed between the start of sending a cycle start packet
and the end of a subaction gap. Bit 21 (cycleMaster) in the link control register is cleared by this event.
24
unrecoverableError
RSCU
This event occurs when the controller encounters any error that forces it to stop operations on any
or all of its subunits, for example, when a DMA context sets its dead bit to 1b. While bit 24 is set to
1b, all normal interrupts for the context(s) that caused this interrupt are blocked from being set to 1b.
23
cycleInconsistent
RSCU
A cycle start was received that had values for the cycleSeconds and cycleCount fields that are
different from the values in bits 3125 (cycleSeconds field) and bits 2412 (cycleCount field) in the
isochronous cycle timer register at OHCI offset F0h (see Section 8.34).
22
cycleLost
RSCU
A lost cycle is indicated when no cycle_start packet is sent or received between two successive
cycleSynch events. A lost cycle can be predicted when a cycle_start packet does not immediately
follow the first subaction gap after the cycleSynch event or if an arbitration reset gap is detected after
a cycleSynch event without an intervening cycle start. Bit 22 may be set to 1b either when a lost cycle
occurs or when logic predicts that one will occur.
21
cycle64Seconds
RSCU
Indicates that the seventh bit of the cycle second counter has changed.
20
cycleSynch
RSCU
Indicates that a new isochronous cycle has started. Bit 20 is set to 1b when the low-order bit of the
cycle count toggles.
19
phy
RSCU
Indicates that the PHY layer requests an interrupt through a status transfer.
18
regAccessFail
RSCU
Indicates that a register access has failed due to a missing SCLK clock signal from the PHY layer.
When a register access fails, bit 18 is set to 1b before the next register access.
Not Recommended for New Designs
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