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| 型號(hào)： | XIO2200AGGW |
| 廠商： | Texas Instruments |
| 文件頁(yè)數(shù)： | 58/202頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-EXPRESS/BUS BRIDGE 176BGA |
| 產(chǎn)品培訓(xùn)模塊： | PCI Express Basics |
| 標(biāo)準(zhǔn)包裝： | 126 |
| 應(yīng)用： | PCI Express 至 PCI 轉(zhuǎn)換橋 |
| 接口： | PCI |
| 電源電壓： | 1.35 V ~ 1.65 V，3 V ~ 3.6 V |
| 封裝/外殼： | 176-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 176-BGA MICROSTAR（15x15） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
| 產(chǎn)品目錄頁(yè)面： | 882 (CN2011-ZH PDF) |
| 配用： | XIO2200AEVM-ND - XIO2200AEVM |
| 其它名稱： | 296-19617 |
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1394 OHCI Memory-Mapped Register Space
137
March 5 2007 June 2011
SCPS154C
8.16 Host Controller Control Register
The host controller control set/clear register pair provides flags for controlling the controller. See Table 811
for a complete description of the register contents.
OHCI register offset:
50h set register
54h clear register
Register type:
Read/Set/Clear/Update, Read/Set/Clear, Read/Clear, Read-only
Default value:
X08X 0000h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
X
0
1
0
X
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
Table 811. Host Controller Control Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
BIBimage Valid
RSU
When bit 31 is set to 1b, the physical response unit is enabled to respond to block read requests
to host configuration ROM and to the mechanism for atomically updating configuration ROM.
Software creates a valid image of the bus_info_block in host configuration ROM before setting
this bit.
When this bit is cleared, the controller returns ack_type_error on block read requests to host
configuration ROM. Also, when this bit is cleared and a 1394 bus reset occurs, the configuration
ROM mapping register at OHCI offset 34h (see Section 8.12), configuration ROM header register
at OHCI offset 18h (see Section 8.7), and bus options register at OHCI offset 20h (see
Section 8.9) are not updated.
Software can set this bit only when bit 17 (linkEnable) is 0b. Once bit 31 is set to 1b, it can be
cleared by a system (hardware) reset, a software reset, or if a fetch error occurs when the
controller loads bus_info_block registers from host memory.
30
noByteSwapData
RSC
Bit 30 controls whether physical accesses to locations outside the controller itself, as well as any
other DMA data accesses are byte swapped.
29
AckTardyEnable
RSC
Bit 29 controls the acknowledgement of ack_tardy. When bit 29 is set to 1b, ack_tardy may be
returned as an acknowledgment to accesses from the 1394 bus to the controller, including
accesses to the bus_info_block. The controller returns ack_tardy to all other asynchronous
packets addressed to the node. When the controller sends ack_tardy, bit 27 (ack_tardy) in the
interrupt event register at OHCI offset 80h/84h (see Section 8.21) is set to 1b to indicate the
attempted asynchronous access.
Software ensures that bit 27 (ack_tardy) in the interrupt event register is 0b. Software also
unmasks wake-up interrupt events such as bit 19 (phy) and bit 27 (ack_tardy) in the interrupt event
register before placing the controller into the D1 power mode.
Software must not set this bit if the node is the 1394 bus manager.
2824
RSVD
R
Reserved. Bits 2824 return 00000b when read.
23
programPhyEnable
R
Bit 23 informs upper-level software that lower-level software has consistently configured the IEEE
1394a-2000 enhancements in the link and PHY layers. When this bit is 1b, generic software such
as the OHCI driver is responsible for configuring IEEE 1394a-2000 enhancements in the PHY
layer and bit 22 (aPhyEnhanceEnable). When this bit is 0b, the generic software may not modify
the IEEE 1394a-2000 enhancements in the PHY layer and cannot interpret the setting of bit 22
(aPhyEnhanceEnable). This bit is initialized from serial EEPROM. This bit defaults to 1b.
22
aPhyEnhanceEnable
RSC
When bits 23 (programPhyEnable) and 17 (linkEnable) are 11b, the OHCI driver can set bit 22
to 1b to use all IEEE 1394a-2000 enhancements. When bit 23 (programPhyEnable) is cleared
to 0b, the software does not change PHY enhancements or this bit.
2120
RSVD
R
Reserved. Bits 21 and 20 return 00b when read.
This bit is reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
Not Recommended for New Designs
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