參數(shù)資料
型號: XCV812E-8FG900C
廠商: Xilinx Inc
文件頁數(shù): 79/118頁
文件大?。?/td> 0K
描述: IC FPGA 1.8V C-TEMP 900-FBGA
產(chǎn)品變化通告: FPGA Family Discontinuation 18/Apr/2011
標準包裝: 1
系列: Virtex®-E EM
LAB/CLB數(shù): 4704
邏輯元件/單元數(shù): 21168
RAM 位總計: 1146880
輸入/輸出數(shù): 556
門數(shù): 254016
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 900-BBGA
供應(yīng)商設(shè)備封裝: 900-FBGA
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-3 (v3.0) March 21, 2014
Module 3 of 4
7
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
IOB Output Switching Characteristics, Figure 1
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
Speed Grade(2)
Units
Description(1)
Symbol
Min3
-8
-7
-6
Propagation Delays
O input to Pad
TIOOP
1.04
2.5
2.7
2.9
ns, max
O input to Pad via transparent latch
TIOOLP
1.24
2.9
3.1
3.4
ns, max
3-State Delays
T input to Pad high-impedance (Note 2)
TIOTHZ
0.73
1.5
1.7
1.9
ns, max
T input to valid data on Pad
TIOTON
1.13
2.7
2.9
3.1
ns, max
T input to Pad high-impedance via
transparent latch (Note 2)
TIOTLPHZ
0.86
1.8
2.0
2.2
ns, max
T input to valid data on Pad via
transparent latch
TIOTLPON
1.26
3.0
3.2
3.4
ns, max
GTS to Pad high impedance (Note 2)
TGTS
1.94
4.1
4.6
4.9
ns, max
Sequential Delays
Clock CLK
Minimum Pulse Width, High
TCH
0.56
1.2
1.3
1.4
ns, min
Minimum Pulse Width, Low
TCL
0.56
1.2
1.3
1.4
ns, min
Clock CLK to Pad
TIOCKP
0.97
2.4
2.8
2.9
ns, max
Clock CLK to Pad high-impedance
(synchronous) (Note 2)
TIOCKHZ
0.77
1.6
2.0
2.2
ns, max
Clock CLK to valid data on Pad
(synchronous)
TIOCKON
1.17
2.8
3.2
3.4
ns, max
Setup and Hold Times before/after
Clock CLK
O input
TIOOCK / TIOCKO
0.43 / 0
0.9 / 0
1.0 / 0
1.1 / 0
ns, min
OCE input
TIOOCECK / TIOCKOCE 0.28 / 0 0.55 / 0.01
0.7 / 0
ns, min
SR input (OFF)
TIOSRCKO / TIOCKOSR 0.40 / 0
0.8 / 0
0.9 / 0
1.0 / 0
ns, min
3-State Setup Times, T input
TIOTCK / TIOCKT
0.26 / 0
0.51 / 0
0.6 / 0
0.7 / 0
ns, min
3-State Setup Times, TCE input
TIOTCECK / TIOCKTCE 0.30 / 0
0.6 / 0
0.7 / 0
0.8 / 0
ns, min
3-State Setup Times, SR input (TFF)
TIOSRCKT / TIOCKTSR 0.38 / 0
0.8 / 0
0.9 / 0
1.0 / 0
ns, min
Set/Reset Delays
SR input to Pad (asynchronous)
TIOSRP
1.30
3.1
3.3
3.5
ns, max
SR input to Pad high-impedance
(asynchronous) (Note 2)
TIOSRHZ
1.08
2.2
2.4
2.7
ns, max
SR input to valid data on Pad
(asynchronous)
TIOSRON
1.48
3.4
3.7
3.9
ns, max
GSR to Pad
TIOGSRQ
3.88
7.6
8.5
9.7
ns, max
Notes:
1.
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
2.
3-state turn-off delays should not be adjusted.
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