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參數(shù)資料
| 型號： | XCV812E-8FG900C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 64/118頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 1.8V C-TEMP 900-FBGA |
| 產(chǎn)品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標準包裝： | 1 |
| 系列： | Virtex®-E EM |
| LAB/CLB數(shù)： | 4704 |
| 邏輯元件/單元數(shù)： | 21168 |
| RAM 位總計： | 1146880 |
| 輸入/輸出數(shù)： | 556 |
| 門數(shù)： | 254016 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 900-BBGA |
| 供應(yīng)商設(shè)備封裝： | 900-FBGA |
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DS025-2 (v3.0) March 21, 2014
Module 2 of 4
1
2000-2014 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Architectural Description
Virtex-E Array
The Virtex-E user-programmable gate array (see Figure 1)
comprises two major configurable elements: configurable
logic blocks (CLBs) and input/output blocks (IOBs).
CLBs provide the functional elements for constructing
logic.
IOBs provide the interface between the package pins
and the CLBs.
CLBs interconnect through a general routing matrix (GRM).
The GRM comprises an array of routing switches located at
the intersections of horizontal and vertical routing channels.
Each CLB nests into a VersaBlock that also provides local
routing resources to connect the CLB to the GRM.
The VersaRing I/O interface provides additional routing
resources around the periphery of the device. This routing
improves I/O routability and facilitates pin locking.
The Virtex-E architecture also includes the following circuits
that connect to the GRM:
Dedicated block memories of 4096 bits each
Clock DLLs for clock-distribution delay compensation
and clock domain control
3-State buffers (BUFTs) associated with each CLB that
drive dedicated segmentable horizontal routing resources
Values stored in static memory cells control the configurable
logic elements and interconnect resources. These values
load into the memory cells on power-up, and can reload if
necessary to change the function of the device.
Input/Output Block
The Virtex-E IOB, Figure 2, features SelectIO+ inputs and
outputs that support a wide variety of I/O signalling stan-
dards (see Table 1).
The three IOB storage elements function either as
edge-triggered D-type flip-flops or as level-sensitive latches.
Each IOB has a clock signal (CLK) shared by the three
flip-flops and independent clock enable signals for each
flip-flop.
0
Virtex-E 1.8 V Extended Memory
Field Programmable Gate Arrays
DS025-2 (v3.0) March 21, 2014
00
Production Product Specification
R
Figure 1: Virtex-E Architecture Overview
DLLDLL
IOBs
VersaRing
ds022_001_121099
CLBs
BRAMs
CLBs
BRAMs
CLBs
DLLDLL
Figure 2: Virtex-E Input/Output Block (IOB)
OBUFT
IBUF
Vref
ds022_02_091300
SR
CLK
ICE
OCE
O
I
IQ
T
TCE
D
CE
Q
SR
D
CE
Q
SR
D
CE
Q
SR
PAD
Programmable
Delay
Weak
Keeper
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV812E-8FG900I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCVR-040L31 | 制造商:WWP 功能描述: |
| XCW 10 | 制造商:G & J HALL 功能描述:COUNTERSINK HEXIBIT 10MM 制造商:G & J HALL 功能描述:COUNTERSINK, HEXIBIT, 10MM 制造商:G & J HALL 功能描述:COUNTERSINK, HEXIBIT, 10MM; Drill Bit Size Metric:10mm; Overall Length:30.5mm; SVHC:No SVHC (19-Dec-2012); Countersink Angle:90; Drill Bit Type:Countersink; Drill Point Diameter:10mm; External Diameter:10mm; Head Diameter:10mm; ;RoHS Compliant: NA |
| XCW10 | 制造商:G & J HALL 功能描述:COUNTERSINK HEXIBIT |
| XCW15 | 制造商:G & J HALL 功能描述:COUNTERSINK HEXIBIT |
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