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參數(shù)資料
| 型號： | XCS40XL-4CS280C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 59/83頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 3.3V C-TEMP 280-CSBGA |
| 標(biāo)準(zhǔn)包裝： | 119 |
| 系列： | Spartan®-XL |
| LAB/CLB數(shù)： | 784 |
| 邏輯元件/單元數(shù)： | 1862 |
| RAM 位總計： | 25088 |
| 輸入/輸出數(shù)： | 224 |
| 門數(shù)： | 40000 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 280-TFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 280-CSBGA（16x16） |
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Spartan and Spartan-XL FPGA Families Data Sheet
62
DS060 (v2.0) March 1, 2013
Product Specification
R
Product Obsolete/Under Obsolescence
Pin Descriptions
There are three types of pins in the Spartan/XL devices:
Permanently dedicated pins
User I/O pins that can have special functions
Unrestricted user-programmable I/O pins.
Before and during configuration, all outputs not used for the
configuration process are 3-stated with the I/O pull-up resis-
tor network activated. After configuration, if an IOB is
unused it is configured as an input with the I/O pull-up resis-
tor network remaining activated.
Any user I/O can be configured to drive the Global
Set/Reset net GSR or the global three-state net GTS. See
Global Signals: GSR and GTS, page 20 for more informa-
tion.
Device pins for Spartan/XL devices are described in
Some Spartan-XL devices are available in Pb-free package
options. The Pb-free package options have the same pin-
outs as the standard package options.
Table 18: Pin Descriptions
Pin Name
I/O
During
Config.
I/O After
Config.
Pin Description
Permanently Dedicated Pins
VCC
X
Eight or more (depending on package) connections to the nominal +5V supply
voltage (+3.3V for Spartan-XL devices). All must be connected, and each must be
decoupled with a 0.01 –0.1
μF capacitor to Ground.
GND
X
Eight or more (depending on package type) connections to Ground. All must be
connected.
CCLK
I or O
I
During configuration, Configuration Clock (CCLK) is an output in Master mode and
is an input in Slave mode. After configuration, CCLK has a weak pull-up resistor
and can be selected as the Readback Clock. There is no CCLK High or Low time
restriction on Spartan/XL devices, except during Readback. See Violating the
for an explanation of this exception.
DONE
I/O
O
DONE is a bidirectional signal with an optional internal pull-up resistor. As an
open-drain output, it indicates the completion of the configuration process. As an
input, a Low level on DONE can be configured to delay the global logic initialization
and the enabling of outputs.
The optional pull-up resistor is selected as an option in the program that creates
the configuration bitstream. The resistor is included by default.
PROGRAM
II
PROGRAM is an active Low input that forces the FPGA to clear its configuration
memory. It is used to initiate a configuration cycle. When PROGRAM goes High,
the FPGA finishes the current clear cycle and executes another complete clear
cycle, before it goes into a WAIT state and releases INIT.
The PROGRAM pin has a permanent weak pull-up, so it need not be externally
pulled up to VCC.
MODE
(Spartan)
M0, M1
(Spartan-XL)
I
X
The Mode input(s) are sampled after INIT goes High to determine the
configuration mode to be used.
During configuration, these pins have a weak pull-up resistor. For the most popular
configuration mode, Slave Serial, the mode pins can be left unconnected. For
Master Serial mode, connect the Mode/M0 pin directly to system ground.
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