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參數(shù)資料
| 型號： | XCS40XL-4CS280C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 18/83頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 3.3V C-TEMP 280-CSBGA |
| 標(biāo)準(zhǔn)包裝： | 119 |
| 系列： | Spartan®-XL |
| LAB/CLB數(shù)： | 784 |
| 邏輯元件/單元數(shù)： | 1862 |
| RAM 位總計(jì)： | 25088 |
| 輸入/輸出數(shù)： | 224 |
| 門數(shù)： | 40000 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 280-TFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 280-CSBGA（16x16） |
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Spartan and Spartan-XL FPGA Families Data Sheet
DS060 (v2.0) March 1, 2013
25
Product Specification
R
Product Obsolete/Under Obsolescence
Power-down retains the configuration, but loses all data
stored in the device flip-flops. All inputs are interpreted as
Low, but the internal combinatorial logic is fully functional.
Make sure that the combination of all inputs Low and all
flip-flops set or reset in your design will not generate internal
oscillations, or create permanent bus contention by activat-
ing internal bus drivers with conflicting data onto the same
long line.
During configuration, the PWRDWN pin must be High. If the
Power Down state is entered before or during configuration,
the device will restart configuration once the PWRDWN sig-
nal is removed. Note that the configuration pins are affected
by Power Down and may not reflect their normal function. If
there is an external pull-up resistor on the DONE pin, it will
be High during Power Down even if the device is not yet
configured. Similarly, if PWRDWN is asserted before config-
uration is completed, the INIT pin will not indicate status
information.
Note that the PWRDWN pin is not part of the Boundary
Scan chain. Therefore, the Spartan-XL family has a sepa-
rate set of BSDL files than the 5V Spartan family. Boundary
scan logic is not usable during Power Down.
Configuration and Test
Configuration is the process of loading design-specific pro-
gramming data into one or more FPGAs to define the func-
tional
operation
of
the
internal
blocks
and
their
interconnections. This is somewhat like loading the com-
mand registers of a programmable peripheral chip.
Spartan/XL devices use several hundred bits of configura-
tion data per CLB and its associated interconnects. Each
configuration bit defines the state of a static memory cell
that controls either a function look-up table bit, a multiplexer
input, or an interconnect pass transistor. The Xilinx develop-
ment system translates the design into a netlist file. It auto-
matically partitions, places and routes the logic and
generates the configuration data in PROM format.
Configuration Mode Control
5V Spartan devices have two configuration modes.
MODE = 1 sets Slave Serial mode
MODE = 0 sets Master Serial mode
3V Spartan-XL devices have three configuration modes.
M1/M0 = 11 sets Slave Serial mode
M1/M0 = 10 sets Master Serial mode
M1/M0 = 0X sets Express mode
In addition to these modes, the device can be configured
through the Boundary Scan logic (See "Configuration
The Mode pins are sampled prior to starting configuration to
determine the configuration mode. After configuration,
these pin are unused. The Mode pins have a weak pull-up
resistor turned on during configuration. With the Mode pins
High, Slave Serial mode is selected, which is the most pop-
ular configuration mode. Therefore, for the most common
configuration mode, the Mode pins can be left unconnected.
If the Master Serial mode is desired, the MODE/M0 pin
should be connected directly to GND, or through a
pull-down resistor of 1 K
Ω or less.
During configuration, some of the I/O pins are used tempo-
rarily for the configuration process. All pins used during con-
Figure 23: PWRDWN Pulse Timing
Power Down Mode
50 ns
TPWDW
TPWD
TPWDW
Outputs
PWRDWN
Description
Power Down Time
Power Down Pulse Width
Symbol
Min
50 ns
DS060_23_041901
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