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參數(shù)資料
| 型號(hào)： | XCS40XL-4CS280C |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 31/83頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 3.3V C-TEMP 280-CSBGA |
| 標(biāo)準(zhǔn)包裝： | 119 |
| 系列： | Spartan®-XL |
| LAB/CLB數(shù)： | 784 |
| 邏輯元件/單元數(shù)： | 1862 |
| RAM 位總計(jì)： | 25088 |
| 輸入/輸出數(shù)： | 224 |
| 門(mén)數(shù)： | 40000 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 280-TFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 280-CSBGA（16x16） |
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Spartan and Spartan-XL FPGA Families Data Sheet
DS060 (v2.0) March 1, 2013
37
Product Specification
R
Product Obsolete/Under Obsolescence
Configuration Through the Boundary Scan
Pins
Spartan/XL devices can be configured through the bound-
ary scan pins. The basic procedure is as follows:
Power up the FPGA with INIT held Low (or drive the
PROGRAM pin Low for more than 300 ns followed by a
High while holding INIT Low). Holding INIT Low allows
enough time to issue the CONFIG command to the
FPGA. The pin can be used as I/O after configuration if
a resistor is used to hold INIT Low.
Issue the CONFIG command to the TMS input.
Wait for INIT to go High.
Sequence the boundary scan Test Access Port to the
SHIFT-DR state.
Toggle TCK to clock data into TDI pin.
The user must account for all TCK clock cycles after INIT
goes High, as all of these cycles affect the Length Count
compare.
For more detailed information, refer to the Xilinx application
note, "Boundary Scan in FPGA Devices." This application
note applies to Spartan and Spartan-XL devices.
Figure 31: Start-up Timing
UCLK_SYNC
UCLK_NOSYNC
CCLK_SYNC
CCLK_NOSYNC
CCLK
GSR Active
UCLK Period
DONE IN
Di
Di+1
Di+2
Di
Di+1
Di+2
U2
U3
U4
U2
U3
U4
U2
U3
U4
C1
Synchronization
Uncertainty
Di
Di+1
Di
Di+1
DONE
I/O
GSR Active
DONE
I/O
GSR Active
DONE
C1
C2
C1
U2
C3
C4
C2
C3
C4
C2
C3
C4
I/O
GSR Active
DONE
I/O
F = Finished, no more
configuration clocks needed
Daisy-chain lead device
must have latest F
Heavy lines describe
default timing
CCLK Period
Length Count Match
F
DS060_39_082801
C1, C2 or C3
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