- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375017 > XCS40 (Xilinx, Inc.) Field Programmable Gate Arrays(現(xiàn)場可編程門陣列) PDF資料下載
參數(shù)資料
| 型號： | XCS40 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Field Programmable Gate Arrays(現(xiàn)場可編程門陣列) |
| 中文描述： | 現(xiàn)場可編程門陣列（現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 49/66頁 |
| 文件大?。?/td> | 716K |
| 代理商： | XCS40 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁當(dāng)前第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁
R
DS060 (v1.5) March 2, 2000
4-49
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan-XL CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines (cont.)
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
Spartan-XL devices and are expressed in nanoseconds unless otherwise noted.
Spartan-XL CLB RAM Synchronous (Edge-Triggered) Write Timing
Dual Port RAM
Speed Grade
-5
-4
Units
Size
1
Symbol
Min
Max
Min
Max
Write Operation
Address write cycle time (clock K period)
Clock K pulse width (active edge)
Address setup time before clock K
DIN setup time before clock K
WE setup time before clock K
All hold times after clock K
Data valid after clock K
16x1
16x1
16x1
16x1
16x1
16x1
16x1
T
WCDS
T
WPDS
T
ASDS
T
DSDS
T
WSDS
T
WODS
7.7
3.1
1.3
1.7
1.4
0.0
5.2
8.4
3.6
1.5
2.0
1.6
0.0
6.1
ns
ns
ns
ns
ns
ns
ns
Note 1: Read Operation Timing for 16x1 dual-port RAM option is identical to 16x2 single-port RAM timing.
WCLK (K)
WE
ADDRESS
DATA IN
T
DSDS
T
DHDS
T
ASDS
T
AHDS
T
WSDS
T
WPDS
T
WHDS
X6474
DATA OUT
OLD
NEW
T
WODS
T
ILO
T
ILO
X6461
WCLK (K)
WE
ADDRESS
DATA IN
DATA OUT
OLD
NEW
T
DSS
T
DHS
T
ASS
T
AHS
T
WSS
T
WPS
T
WHS
T
WOS
T
ILO
T
ILO
Single Port
Dual Port
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCS40XL | Field Programmable Gate Arrays(現(xiàn)場可編程門陣列) |
| XCV1000E-6FG900C | Field Programmable Gate Arrays |
| XCV600E-8HQ240C | Virtex-E 1.8 V Field Programmable Gate Arrays |
| XCV600E-8HQ240I | Virtex-E 1.8 V Field Programmable Gate Arrays |
| XCV1000E-6FG860C | Virtex⑩-E 1.8 V Field Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCS40-3BG100C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS40-3BG100I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS40-3BG144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS40-3BG144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS40-3BG208C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。