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參數(shù)資料
| 型號： | XCS40 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Field Programmable Gate Arrays(現(xiàn)場可編程門陣列) |
| 中文描述： | 現(xiàn)場可編程門陣列（現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 46/66頁 |
| 文件大小： | 716K |
| 代理商： | XCS40 |
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R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
4-46
DS060 (v1.5) March 2, 2000
Spartan-XL Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven
from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting
the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System)
and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static
timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction
temperature).
Speed Grade
Description
From pad through buffer, to any clock K
-5
-4
Units
Symbol
T
GLS
Device
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
Max
1.4
1.7
2.0
2.3
2.6
Max
1.5
1.8
2.1
2.5
2.8
ns
ns
ns
ns
ns
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