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參數(shù)資料
| 型號： | XCS30XL-4VQG100C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 21/83頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SPARTAN-XL FPGA 30K 100-VQFP |
| 產(chǎn)品變化通告： | Product Discontinuation 26/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | Spartan®-XL |
| LAB/CLB數(shù)： | 576 |
| 邏輯元件/單元數(shù)： | 1368 |
| RAM 位總計： | 18432 |
| 輸入/輸出數(shù)： | 77 |
| 門數(shù)： | 30000 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 100-TQFP |
| 供應(yīng)商設(shè)備封裝： | 100-VQFP（14x14） |
| 產(chǎn)品目錄頁面： | 599 (CN2011-ZH PDF) |
| 其它名稱： | 122-1299 |
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Spartan and Spartan-XL FPGA Families Data Sheet
28
DS060 (v2.0) March 1, 2013
Product Specification
R
Product Obsolete/Under Obsolescence
Slave Serial is the default mode if the Mode pins are left
unconnected, as they have weak pull-up resistors during
configuration.
Multiple slave devices with identical configurations can be
wired with parallel DIN inputs. In this way, multiple devices
can be configured simultaneously.
Serial Daisy Chain
Multiple devices with different configurations can be con-
nected together in a "daisy chain," and a single combined
bitstream used to configure the chain of slave devices.
To configure a daisy chain of devices, wire the CCLK pins of
all devices in parallel, as shown in Figure 25. Connect the
DOUT of each device to the DIN of the next. The lead or
master FPGA and following slaves each passes resynchro-
nized configuration data coming from a single source. The
header data, including the length count, is passed through
and is captured by each FPGA when it recognizes the 0010
preamble. Following the length-count data, each FPGA out-
puts a High on DOUT until it has received its required num-
ber of data frames.
After an FPGA has received its configuration data, it passes
on any additional frame start bits and configuration data on
DOUT. When the total number of configuration clocks
applied after memory initialization equals the value of the
24-bit length count, the FPGAs begin the start-up sequence
and become operational together. FPGA I/O are normally
released two CCLK cycles after the last configuration bit is
received.
The daisy-chained bitstream is not simply a concatenation
of the individual bitstreams. The PROM File Formatter must
be used to combine the bitstreams for a daisy-chained con-
figuration.
Figure 25: Master/Slave Serial Mode Circuit Diagram
Spartan
Master
Seria
l
Spartan
Slave
FPGA
Slave
Xilinx SPROM
PROGRAM
Note:
M2, M1, M0 can be shorted
to VCC if not used as I/O
MODE
DOUT
CCLK
CLK
VCC
+5V
DATA
CE
CEO
VPP
RESET/OE
DONE
DIN
LDC
INIT
DONE
PROGRAM
D/P
INIT
RESET
CCLK
DIN
CCLK
DIN
DOUT
MODE
M1
M0
M2
(Low Reset Option Used)
3.3K
DS060_25_061301
N/C
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