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| 型號： | XCS30-4TQ100C |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴達和Spartan - xL的家庭現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 60/82頁 |
| 文件大小： | 623K |
| 代理商： | XCS30-4TQ100C |
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
60
www.xilinx.com
1-800-255-7778
DS060 (v1.6) September 19, 2001
Product Specification
R
Spartan-XL IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature).
Symbol
Device
Speed Grade
Units
-5
-4
Description
Min
Max
Min
Max
Setup Times
T
ECIK
T
PICK
T
POCK
Hold Times
Clock Enable (EC) to Clock (IK)
All devices
0.0
-
0.0
-
ns
Pad to Clock (IK), no delay
All devices
1.0
-
1.2
-
ns
Pad to Fast Capture Latch Enable (OK), no delay
All devices
0.7
-
0.8
-
ns
All Hold Times
All devices
0.0
-
0.0
-
ns
Propagation Delays
T
PID
T
PLI
T
IKRI
T
IKLI
Delay Adder for Input with Full Delay Option
Pad to I1, I2
All devices
-
0.9
-
1.1
ns
Pad to I1, I2 via transparent input latch, no delay
All devices
-
2.1
-
2.5
ns
Clock (IK) to I1, I2 (flip-flop)
All devices
-
1.0
-
1.1
ns
Clock (IK) to I1, I2 (latch enable, active Low)
All devices
-
1.1
-
1.2
ns
T
Delay
T
PICKD
= T
PICK
+ T
Delay
T
PDLI
= T
PLI
+ T
Delay
XCS05XL
4.0
-
4.7
-
ns
XCS10XL
4.8
-
5.6
-
ns
XCS20XL
5.0
-
5.9
-
ns
XCS30XL
5.5
-
6.5
-
ns
XCS40XL
6.5
-
7.6
-
ns
Global Set/Reset
T
MRW
T
RRI
Minimum GSR pulse width
All devices
10.5
-
11.5
-
ns
Delay from GSR input to any Q
XCS05XL
-
9.0
-
10.5
ns
XCS10XL
-
9.5
-
11.0
ns
XCS20XL
-
10.0
-
11.5
ns
XCS30XL
-
11.0
-
12.5
ns
XCS40XL
-
12.0
-
13.5
ns
Notes:
1.
Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock
input, see the pin-to-pin parameters in the Pin-to-Pin Input Parameters table.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
2.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCS30-4TQ100I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS30-4TQ144C | 功能描述:IC FPGA 5V C-TEMP 144-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan® 標準包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應商設備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XCS30-4TQ144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS30-4TQ208C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS30-4TQ208I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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