參數(shù)資料
型號(hào)： XCS30-4TQ100C
廠商： Xilinx, Inc.
英文描述： Spartan and Spartan-XL Families Field Programmable Gate Arrays
中文描述： 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場(chǎng)可編程門(mén)陣列
文件頁(yè)數(shù)： 34/82頁(yè)
文件大?。?/td> 623K
代理商： XCS30-4TQ100C
Spartan and Spartan-XL Families Field Programmable Gate Arrays
34
www.xilinx.com
1-800-255-7778
DS060 (v1.6) September 19, 2001
Product Specification
R
Configuration Sequence
There are four major steps in the Spartan/XL power-up con-
figuration sequence.
Configuration Memory Clear
Initialization
Configuration
Start-up
The full process is illustrated in
Figure 30
.
Configuration Memory Clear
When power is first applied or is reapplied to an FPGA, an
internal circuit forces initialization of the configuration logic.
When V
CC
reaches an operational level, and the circuit
passes the write and read test of a sample pair of configu-
ration bits, a time delay is started. This time delay is nomi-
nally 16 ms. The delay is four times as long when in Master
Serial Mode to allow ample time for all slaves to reach a sta-
ble V
CC
. When all INIT pins are tied together, as recom-
mended, the longest delay takes precedence. Therefore,
devices with different time delays can easily be mixed and
matched in a daisy chain.
This delay is applied only on power-up. It is not applied
when reconfiguring an FPGA by pulsing the PROGRAM pin
Low. During this time delay, or as long as the PROGRAM
input is asserted, the configuration logic is held in a Config-
uration Memory Clear state. The configuration-memory
frames are consecutively initialized, using the internal oscil-
lator.
At the end of each complete pass through the frame
addressing, the power-on time-out delay circuitry and the
level of the PROGRAM pin are tested. If neither is asserted,
the logic initiates one additional clearing of the configuration
frames and then tests the INIT input.
Initialization
During initialization and configuration, user pins HDC, LDC,
INIT and DONE provide status outputs for the system inter-
face. The outputs LDC, INIT and DONE are held Low and
HDC is held High starting at the initial application of power.
The open drain INIT pin is released after the final initializa-
tion pass through the frame addresses. There is a deliber-
ate delay before a Master-mode device recognizes an
inactive INIT. Two internal clocks after the INIT pin is recog-
nized as High, the device samples the MODE pin to deter-
mine the configuration mode. The appropriate interface
lines become active and the configuration preamble and
data can be loaded.
Figure 29:
Circuit for Generating CRC-16
0
X2
2
3
4
5
6
7
8
9 10 11 12 13 14
1
X15
X16
15
SERIAL DATA IN
1
0 15 14 13 12 11 10 9
8
7
6
5
1
1
1
1
CRC
–
CHECKSUM
LAST DATA FRAME
S
DS060_29_080400
Polynomial: X16 + X15 + X2 + 1
Readback Data Stream
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