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參數(shù)資料
| 型號(hào)： | XCS20-4TQ144C |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | FPGA, 400 CLBS, 7000 GATES, 166 MHz, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁數(shù)： | 51/83頁 |
| 文件大小： | 770K |
| 代理商： | XCS20-4TQ144C |
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Spartan and Spartan-XL FPGA Families Data Sheet
DS060 (v1.8) June 26, 2008
55
Product Specification
R
Spartan-XL Family CLB Switching Characteristic Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
the simulation netlist. All timing parameters assume
worst-case operating conditions (supply voltage and junc-
tion temperature). Values apply to all Spartan-XL devices
and expressed in nanoseconds unless otherwise noted.
Symbol
Description
Speed Grade
Units
-5
-4
MinMax
Clocks
TCH
Clock High time
2.0
-
2.3
-
ns
TCL
Clock Low time
2.0
-
2.3
-
ns
Combinatorial Delays
TILO
F/G inputs to X/Y outputs
-
1.0
-
1.1
ns
TIHO
F/G inputs via H to X/Y outputs
-
1.7
-
2.0
ns
TITO
F/G inputs via transparent latch to Q outputs
-
1.5
-
1.8
ns
THH1O
C inputs via H1 via H to X/Y outputs
-
1.5
-
1.8
ns
Sequential Delays
TCKO
Clock K to Flip-Flop or latch outputs Q
-
1.2
-
1.4
ns
Setup Time before Clock K
TICK
F/G inputs
0.6
-
0.7
-
ns
TIHCK
F/G inputs via H
1.3
-
1.6
-
ns
Hold Time after Clock K
All Hold times, all devices
0.0
-
0.0
-
ns
Set/Reset Direct
TRPW
Width (High)
2.5
-
2.8
-
ns
TRIO
Delay from C inputs via S/R, going High to Q
-
2.3
-
2.7
ns
Global Set/Reset
TMRW
Minimum GSR Pulse Width
10.5
-
11.5
-
ns
TMRQ
Delay from GSR input to any Q
FTOG
Toggle Frequency (MHz)
(for export control purposes)
-
250
-
217
MHz
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| XCS20-4TQ144C0262 | 制造商:Xilinx 功能描述: |
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