參數(shù)資料
型號(hào)： XCS20-4TQ144C
廠(chǎng)商： XILINX INC
元件分類(lèi)： FPGA
英文描述： Spartan and Spartan-XL Families Field Programmable Gate Arrays
中文描述： FPGA, 400 CLBS, 7000 GATES, 166 MHz, PQFP144
封裝： PLASTIC, TQFP-144
文件頁(yè)數(shù)： 46/83頁(yè)
文件大?。?/td> 770K
代理商： XCS20-4TQ144C
Spartan and Spartan-XL FPGA Families Data Sheet
50
DS060 (v1.8) June 26, 2008
Product Specification
R
Spartan Family IOB Input Switching Characteristic Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
the simulation netlist. These path delays, provided as a
guideline, have been extracted from the static timing ana-
lyzer report. All timing parameters assume worst-case oper-
ating conditions (supply voltage and junction temperature).
Symbol
Description
Device
Speed Grade
Units
-4
-3
Min
Max
Min
Max
Setup Times - TTL Inputs(1)
TECIK
Clock Enable (EC) to Clock (IK), no delay
All devices
1.6
-
2.1
-
ns
TPICK
Pad to Clock (IK), no delay
All devices
1.5
-
2.0
-
ns
Hold Times
TIKEC
Clock Enable (EC) to Clock (IK), no delay
All devices
0.0
-
0.9
-
ns
All Other Hold Times
All devices
0.0
-
0.0
-
ns
Propagation Delays - TTL Inputs(1)
TPID
Pad to I1, I2
All devices
-
1.5
-
2.0
ns
TPLI
Pad to I1, I2 via transparent input latch, no delay
All devices
-
2.8
-
3.6
ns
TIKRI
Clock (IK) to I1, I2 (flip-flop)
All devices
-
2.7
-
2.8
ns
TIKLI
Clock (IK) to I1, I2 (latch enable, active Low)
All devices
-
3.2
-
3.9
ns
Delay Adder for Input with Delay Option
TDelay
TECIKD = TECIK + TDelay
TPICKD = TPICK + TDelay
TPDLI = TPLI + TDelay
XCS05
3.6
-
4.0
-
ns
XCS10
3.7
-
4.1
-
ns
XCS20
3.8
-
4.2
-
ns
XCS30
4.5
-
5.0
-
ns
XCS40
5.5
-
5.5
-
ns
Global Set/Reset
TMRW
Minimum GSR pulse width
All devices
11.5
-
13.5
-
ns
TRRI
Delay from GSR input to any Q
XCS05
-
9.0
-
11.3
ns
XCS10
-
9.5
-
11.9
ns
XCS20
-
10.0
-
12.5
ns
XCS30
-
10.5
-
13.1
ns
XCS40
-
11.0
-
13.8
ns
Notes:
1.
Delay adder for CMOS Inputs option: for -3 speed grade, add 0.4 ns; for -4 speed grade, add 0.2 ns.
2.
Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock
input, see the pin-to-pin parameters in the Pin-to-Pin Input Parameters table.
3.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
相關(guān)PDF資料
PDF描述
XCS20XL-4PQ208C Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS20XL-5CS144C Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS20XL-5PQ208C Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS20XL-5TQ144C Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS30-4BG256C Spartan and Spartan-XL Families Field Programmable Gate Arrays
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XCS20-4TQ144C0262 制造商:Xilinx 功能描述:
XCS20-4TQ144I 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS20-4TQ208C 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS20-4TQ208I 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS20-4TQ240C 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*