參數(shù)資料
型號(hào)： XCS05XL-3CS208I
廠商： Xilinx, Inc.
英文描述： Spartan and Spartan-XL Families Field Programmable Gate Arrays
中文描述： 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場(chǎng)可編程門陣列
文件頁(yè)數(shù)： 31/66頁(yè)
文件大?。?/td> 809K
代理商： XCS05XL-3CS208I
R
DS060 (v1.5) March 2, 2000
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4-31
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Delaying Configuration After Power-Up
There are two methods of delaying configuration after
power-up: put a logic Low on the PROGRAM input, or pull
the bidirectional INIT pin Low, using an open-collector
(open-drain) driver. (See
Figure 30 on page 30
.)
A Low on the PROGRAM input is the more radical
approach, and is recommended when the power-supply
rise time is excessive or poorly defined. As long as PRO-
GRAM is Low, the FPGA keeps clearing its configuration
memory. When PROGRAM goes High, the configuration
memory is cleared one more time, followed by the begin-
ning of configuration, provided the INIT input is not exter-
nally held Low. Note that a Low on the PROGRAM input
automatically forces a Low on the INIT output. The Spar-
tan/XL PROGRAM pin has a permanent weak pull-up.
Avoid holding PROGRAM Low for more than 500
μ
s.
Using an open-collector or open-drain driver to hold INIT
Low before the beginning of configuration causes the
FPGA to wait after completing the configuration memory
clear operation. When INIT is no longer held Low externally,
the device determines its configuration mode by capturing
the state of the Mode pins, and is ready to start the config-
uration process. A master device waits up to an additional
300
μ
s to make sure that any slaves in the optional daisy
chain have seen that INIT is High.
Configuration Through the Boundary Scan
Pins
Spartan/XL devices can be configured through the bound-
ary scan pins. The basic procedure is as follows:
Power up the FPGA with INIT held Low (or drive the
PROGRAM pin Low for more than 300 ns followed by a
High while holding INIT Low). Holding INIT Low allows
enough time to issue the CONFIG command to the
FPGA. The pin can be used as I/O after configuration if
a resistor is used to hold INIT Low.
Issue the CONFIG command to the TMS input
Wait for INIT to go High
Sequence the boundary scan Test Access Port to the
SHIFT-DR state
Toggle TCK to clock data into TDI pin.
The user must account for all TCK clock cycles after INIT
goes High, as all of these cycles affect the Length Count
compare.
For more detailed information, refer to the Xilinx application
note, "
Boundary Scan in FPGA Devices
." This application
note applies to Spartan and Spartan-XL devices.
相關(guān)PDF資料
PDF描述
XCS05XL-3CS240C Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS05XL-3CS240I Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS05XL-3CS256C Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS05XL-3CS256I Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS05XL-3CS280C Spartan and Spartan-XL Families Field Programmable Gate Arrays
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XCS05XL-3CS240C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS05XL-3CS240I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS05XL-3CS256C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS05XL-3CS256I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS05XL-3CS280C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
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