- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372881 > XCR3384XLSERIES 384 Macrocell CPLD PDF資料下載
參數(shù)資料
| 型號： | XCR3384XLSERIES |
| 英文描述： | 384 Macrocell CPLD |
| 中文描述： | 384宏單元CPLD |
| 文件頁數(shù)： | 2/43頁 |
| 文件大小： | 396K |
| 代理商： | XCR3384XLSERIES |
第1頁當(dāng)前第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁
The XCR3320 CPLDs are supported by industry standard
CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor, Syn-
opsys, Synario, Viewlogic, and Synplicity), using text
(ABEL, VHDL, Verilog) and/or schematic entry. Design ver-
ification uses industry standard simulators for functional
and timing simulation. Development is supported on per-
sonal computer, Sparc, and HP platforms. Device fitting
uses a Xilinx developed tool including WebFITTER.
XPLA2 Architecture
Figure 1
shows a high level block diagram of the XCR3320
implementing the XPLA2 architecture. The XPLA2 archi-
tecture is a multi-level, modular hierarchy that consists of
Fast Modules interconnected by a virtual crosspoint switch
called the Global Zero Power Interconnect Array (GZIA).
Each Fast Module accepts 64 bits from the GZIA and out-
puts 64 bits to the GZIA. Each Fast Module is essentially an
80 macrocell CPLD with four logic blocks of 20 macrocells
each inside. There are eight dedicated, low-skew, global
clocks for the device; and each Fast Module has access to
any two of these clocks (there are additional asynchronous
clocks available in the Fast Modules, see
Figure 3
. There
are also Global 3-state (gts) and Global Reset (rstn) pins
that are common to all Fast Modules. When gts is pulled
high, all output buffers in the device will be disabled, caus-
ing all I/O pins to be tri-stated. When rstn is pulled low, all
flip-flops of the device will be reset.
Figure 1: Xilinx XPLA2 CPLD Architecture
reset/OE
SP00665
EEPROM
CE
dout
cclk
din
SLAVE #2
pgrmn
resetn
M2
M1
M0
crcerrn
dout
hdc
cclk
done
M3
V
CC
V
CC
cclk
din
SLAVE #1
pgrmn
resetn
M2
M1
M0
crcerrn
dout
hdc
done
M3
V
CC
cclk
din
MASTER SERIAL
LEAD
pgrmn
resetn
M2
M1
M0
crcerrn
dout
hdc
done
M3
V
CC
V
CC
V
CC
Powered by ICminer.com Electronic-Library Service CopyRight 2003
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCS05XL-4PC84C | Field Programmable Gate Array (FPGA) |
| XCS05XL-5PC84C | Field Programmable Gate Array (FPGA) |
| XCS05-3PC84 | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05 | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3BG240C | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCR3512XL | 制造商:XILINX 制造商全稱:XILINX 功能描述:CoolRunner XPLA3 CPLD |
| XCR3512XL-10FG324C | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 12K GATES 512 MCRCLLS 125MHZ 0.35UM 3. - Trays |
| XCR3512XL-10FG324I | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 12K GATES 512 MCRCLLS 125MHZ 0.35UM 3. - Trays |
| XCR3512XL-10FGG324C | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 12K GATES 512 MCRCLLS 125MHZ 0.35UM 3. - Trays |
| XCR3512XL-10FGG324I | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 12K GATES 512 MCRCLLS 125MHZ 0.35UM 3. - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。