
R
XCR3320: 320 Macrocell SRAM CPLD
31
1-800-255-7778DS033 (v1.1) February 10, 2000
AC Electrical Characteristics For Commercial Grade Devices
Commercial temperature range: V
CC
= 3.0V to 3.6V; 0
°
C < T
AMB
< 70
°
C
Symbol
Parameter
C7
C10
Unit
Min. Max. Min. Max.
Timing Requirements
t
CL
Clock LOW time
t
CH
Clock HIGH time
t
SU_PAL
PAL setup time (Global clock)
t
SU_PLA
PLA setup time (Global clock)
t
SU_XOR
XOR setup time (Global clock)
t
H
Hold time (Global clock)
Output Characteristics
t
PD_PAL
Input to output delay through PAL
t
PD_PLA
Input to output delay through PLA
t
PD_XOR
Input to output delay through XOR
t
PDF_PAL
Input (or feedback node) to internal feedback node delay time through
PAL
t
PDF_PLA
Input (or feedback node) to internal feedback node delay time through
PLA
t
PDF_XOR
Input (or feedback node) to internal feedback node delay time through
XOR
t
CF
Global clock to feedback delay
t
CO
Global clock to out delay
t
CS
Clock skew (variance for switching outputs with common global clock)
f
MAX1
Maximum flip-flop toggle rate:
2.5
2.5
3.0
4.5
5.5
3.0
3.0
4.0
5.5
6.5
ns
ns
ns
ns
ns
ns
0
0
7.5
9.0
10.0
4.5
10.0
11.5
12.5
6.0
ns
ns
ns
ns
6.0
7.5
ns
7.0
8.5
ns
3.0
6.0
1.0
3.5
7.5
1.5
ns
ns
ns
MHz
200
166
f
MAX2
Maximum internal frequency:
166
133
MHz
f
MAX3
Maximum external frequency:
111
87
MHz
t
BUFF
t
SSR
t
EA
t
ER
t
GTSA
t
GTSR
t
RR
t
RP
t
GRR
t
GZIA
Note
:
Output buffer delay (fast)
Slow slew rate incremental delay
Output enable delay
Output disable delay
1
Global 3-state enable
Global 3-state disable
Input to register reset
Input to register preset
Global reset to register reset
Global ZIA delay
3.0
5.0
4.0
6.0
ns
ns
10.0
10.0
10.0
10.0
10.5
9.5
10
2.0
12.0
12.0
12.0
12.0
12.0
11.0
12.0
2.5
ns
ns
ns
ns
ns
ns
ns
ns
1. Output C
L
= 5.0 pF.
+
t
CL
t
CH
-------1
t
SU
PAL
–
t
CF
+
------------1
t
SU
PAL
–
t
CO
+
-------------1
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