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| 型號： | XCR3320-10TQ144C |
| 文件頁數(shù)： | 22/43頁 |
| 文件大小： | 396K |
| 代理商： | XCR3320-10TQ144C |
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Slave Parallel Mode
The slave parallel mode is essentially the same as the syn-
chronous peripheral mode, except that the chip select pins
(cs1 and cs0n) are not used. As in the synchronous periph-
eral mode, byte-wide data is input into D[7:0] on the rising
edge of the cclk input. The first data byte is clocked in on
the second cclk after hdc goes High. Subsequent data
bytes are clocked in on every eighth rising edge of cclk. The
process repeats until all of the data is loaded into the
XCR3320. The serial data begins shifting out on dout 0.5
cycles after the parallel data was loaded. It requires addi-
tional cclks after the last byte is loaded to complete the
shifting.
Figure 25
shows the interface for slave parallel
mode. When configuring a single device, the frequency of
cclk can be up to 10 MHz.
As with synchronous peripheral mode, the slave parallel
mode can be used as the lead XCR3320 for daisy-chained
devices. Note that the cclk frequency for daisy-chain oper-
ation is limited to 1 MHz.
Table 8: Slave Serial Configuration Mode Timing Characteristics
Symbol
t
S
t
H
t
CH
Parameter
Min
20
0
50
500
50
500
-
-
Max.
0
-
-
-
-
-
10
1
Unit
ns
ns
ns
ns
ns
ns
MHz
MHz
din setup time
din hold time
cclk high time
Single device
Daisy-chain device
Single device
Daisy-chain device
Single device
Daisy-chain device
t
CL
cclk low time
f
C
cclk frequency
SP00669
MICRO
–
PROCESSOR
crcerrn
prgmn
done
cclk
M2
M1
M0
WRN
CS0N
V
CC
dout
TO DAISY
–
CHAINED
DEVICES
D[7:0]
8
XCR3320
M3
CS1
resetn
EXTERNALLY CONTROLLED
IF DESIRED
V
CC
Figure 25: Slave Parallel Configuration Schematic
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