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參數(shù)資料
| 型號(hào)： | XCR3256XL-7PQ208C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPLD 256MCELL 3.3V HP 208PQFP |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | CoolRunner XPLA3 |
| 可編程類型： | 系統(tǒng)內(nèi)可編程（最少 1K 次編程/擦除循環(huán)） |
| 最大延遲時(shí)間 tpd(1)： | 7.0ns |
| 電壓電源 - 內(nèi)部： | 3 V ~ 3.6 V |
| 邏輯元件/邏輯塊數(shù)目： | 16 |
| 宏單元數(shù)： | 256 |
| 門數(shù)： | 6000 |
| 輸入/輸出數(shù)： | 164 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 208-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 208-PQFP（28x28） |
| 包裝： | 托盤 |
CoolRunner XPLA3 CPLD
2
DS012 (v2.5) May 26, 2009
Product Specification
R
Family Overview
The CoolRunner XPLA3 (eXtended Programmable Logic
Array) family of CPLDs is targeted for low power systems
that include portable, handheld, and power sensitive appli-
cations. Each member of the CoolRunner XPLA3 family
includes Fast Zero Power (FZP) design technology that
combines low power and high speed. With this design tech-
nique, the CoolRunner XPLA3 family offers true pin-to-pin
speeds of 5.0 ns, while simultaneously delivering power
that is less than 56
μW at standby without the need for
"turbo bits" or other power down schemes. By replacing
conventional sense amplifier methods for implementing
product terms (a technique that has been used in PLDs
since the bipolar era) with a cascaded chain of pure CMOS
gates, the dynamic power is also substantially lower than
any other CPLD. CoolRunner devices are the only TotalC-
MOS PLDs, as they use both a CMOS process technology
and the patented full CMOS FZP design technique. The
FZP design technique combines fast nonvolatile memory
cells with ultra-low power SRAM shadow memory to deliver
the industry’s lowest power 3.3V CPLD family.
The CoolRunner XPLA3 family employs a full PLA structure
for logic allocation within a function block. The PLA provides
maximum flexibility and logic density, with superior pin lock-
ing capability, while maintaining deterministic timing.
CoolRunner
XPLA3
CPLDs
are
supported
by
Xilinx WebPACK software and industry standard CAE
tools (Mentor, Cadence/OrCAD, Exemplar Logic, Synopsys,
Viewlogic, and Synplicity), using HDL editors with ABEL,
VHDL, and Verilog, and/or schematic capture design entry.
Design verification uses industry standard simulators for
functional and timing simulation. Development is supported
on multiple personal computer (PC), Sun, and HP plat-
forms.
The CoolRunner XPLA3 family features also include the
industry-standard, IEEE 1149.1, JTAG interface through
which boundary-scan testing, In-System Programming
(ISP), and reprogramming of the device can occur. The
CoolRunner XPLA3 CPLD is electrically reprogrammable
using industry standard device programmers.
CoolRunner XPLA3 Architecture
Figure 1 shows a high-level block diagram of a 128 macro-
cell device implementing the CoolRunner XPLA3 architec-
ture. The CoolRunner XPLA3 architecture consists of
function blocks that are interconnected by a Zero-power
Interconnect Array (ZIA). The ZIA is a virtual crosspoint
switch. Each function block has 40 inputs from the ZIA and
contains 16 macrocells.
From this point of view, this architecture looks like many
other CPLD architectures. What makes the CoolRunner
XPLA3 family unique is logic allocation inside each function
block, and the design technique used to implement product
terms.
Function Block Architecture
Figure 3 illustrates the function block architecture. Each
function block contains a PLA array that generates control
terms, clock terms, and logic cells. A PLA differs from a PAL
in that the PLA has a fully programmable AND array fol-
lowed by a fully programmable OR array. A PAL array has a
fixed OR array, limiting flexibility. Refer to Figure 2 for an
example of a PAL and a PLA array. The PLA array receives
its inputs directly from the ZIA. There are 40 pairs of true
and complement inputs from the ZIA that feed the 48 prod-
uct terms in the array. Within the 48 P-terms there are eight
local control terms (LCT[0:7]) available as control signals to
each macrocell for use as asynchronous clocks, resets, pre-
sets and output enables. If not needed as control terms,
these P-Terms can join the other 40 P-Terms as additional
logic resources.
In each function block there are eight foldback NAND prod-
uct terms that can be used to synthesize increased logic
density in support of wider logic equations. This feature can
be disabled in software by the user. As with unused control
P-Terms, unused foldback NAND P-Terms can be used as
additional logic resources.
Sixteen high-speed P-Terms are available at each macro-
cell for speed critical logic. If wider than a single P-Term
logic is required at a macrocell, 47 additional P-Terms can
be summed in prior to the VFM (Variable Function Multi-
plexer). The VFM increases logic optimization by imple-
menting some two input logic functions before entering the
macrocell (see Figure 4).
Each macrocell can support combinatorial or registered
logic. The macrocell register accommodates asynchronous
presets and resets, and "power on" initial state. A hardware
clock enable is also provided for either D or T type registers,
and the register clock input is used as a latch enable when
the macrocell register is configured as a latch function.
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