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| 型號： | XCR3128XLSERIES |
| 英文描述： | 128 Macrocell CPLD |
| 中文描述： | 128個宏單元CPLD |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 91K |
| 代理商： | XCR3128XLSERIES |
XCR3128XL 128 Macrocell CPLD
DS016 (v1.8) January 8, 2002
Preliminary Product Specification
1-800-255-77783
R
AC Electrical Characteristics Over Recommended Operating Conditions
(1,2)
Symbol
T
PD1
T
PD2
T
CO
T
SUF
T
SU1(4)
T
SU2
T
H(4)
T
WLH(4)
Tt
PLH(4)
T
R(4)
T
L(4)
f
SYSTEM(4)
T
CONFIG(4)
T
INIT(4)
T
POE(4)
T
POD(4)
T
PCO(4)
T
PAO(4)
Parameter
-6
-7
-10
Unit
ns
Min.
-
Max.
5.5
Min.
-
Max.
7.0
Min.
-
Max.
9.1
Propagation delay time (single p-term)
Propagation delay time (OR array)
(3)
-
6.0
-
7.5
-
10.0
ns
Clock to output (global synchronous pin clock)
-
4.0
5.0
-
6.5
ns
Setup time (fast input register)
Setup time (single p-term)
2.5
3.5
-
-
3.0
4.3
-
-
3.0
5.4
-
-
ns
ns
Setup time (OR array)
4.0
-
4.8
-
6.3
-
ns
Hold time
0
-
0
-
0
-
ns
Global Clock pulse width (High or Low)
P-term clock pulse width
2.5
4.0
-
-
3.0
5.0
-
-
4.0
6.0
-
-
ns
ns
Input rise time
-
20
-
20
-
20
ns
Input fall time
-
20
-
20
-
20
ns
Maximum system frequency
Configuration time
(5)
-
-
145
60
-
-
119
60
-
-
95
60
MHz
μ
s
μ
s
ns
ISP initialization time
-
60
-
60
-
60
P-term OE to output enabled
P-term OE to output disabled
(6)
P-term clock to output
-
7.5
-
9.3
-
11.2
-
-
7.5
6.5
-
-
9.3
8.3
-
-
11.2
10.7
ns
ns
P-term set/reset to output valid
-
8.0
-
9.3
-
11.2
ns
Advance
Preliminary
Notes:
1.
2.
3.
4.
5.
6.
Specifications measured with one output switching.
See XPLA3 family data sheet (
DS012
) for recommended operating conditions.
See
Figure 4
for derating.
These parameters guaranteed by design and/or characterization, not testing.
Typical current draw during configuration is 9 mA at 3.6V.
Output C
L
= 5 pF.
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