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參數(shù)資料
| 型號： | XCR3128XLSERIES |
| 英文描述： | 128 Macrocell CPLD |
| 中文描述： | 128個宏單元CPLD |
| 文件頁數(shù)： | 10/10頁 |
| 文件大?。?/td> | 91K |
| 代理商： | XCR3128XLSERIES |
R
Revision History
The following table shows the revision history for this document.
Date
Version
Revision
04/07/00
1.0
Initial Xilinx release.
05/03/00
1.1
Minor updates and added Boundary Scan to pinout table.
11/20/00
1.2
Updated pinout tables; corrected note in
Table 4
to read: "port enable pin is brought High".
12/08/00
1.3
Updated pinout tables.
01/17/01
1.4
Removed Timing Model.
04/11/01
1.5
Added Typical I/V curve,
Figure 2
; added
Table 2
: Total User I/O; changed V
OH
spec.
Updated Typical I/V curve,
Figure 2
: added voltage levels.
04/19/01
1.6
08/10/01
1.7
Moved
Figure 1
and
Table 1
to first page. Changed VQ144 to VQ100 in
Table 2
.
01/08/02
1.8
Updated T
SUF
and T
FIN
spec to match software timing. Added single p-term setup time
(T
SU1
) to AC Table, renamed T
SU
to T
SU2
for setup time through the OR array. Added T
INIT
spec. Updated T
CONFIG
spec. Updated T
HI
spec to correct a typo. Updated AC Load Circuit
diagram to more closely resemble true test conditions, added note for T
POD
delay
measurement.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCR3256XLSERIES | 256 Macrocell CPLD |
| XCR3320-10TQ144C | |
| XCR3320-7TQ144C | |
| XCR3320-8TQ144I | |
| XCR3384XLSERIES | 384 Macrocell CPLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCR3256XL | 制造商:XILINX 制造商全稱:XILINX 功能描述:256 Macrocell CPLD |
| XCR3256XL_03 | 制造商:XILINX 制造商全稱:XILINX 功能描述:256 Macrocell CPLD |
| XCR3256XL-10CS280C | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 6K GATES 256 MCRCLLS 125MHZ 0.35UM 3.3 - Trays |
| XCR3256XL-10CS280I | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 6K GATES 256 MCRCLLS 125MHZ 0.35UM 3.3 - Trays |
| XCR3256XL-10CSG280C | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 6K GATES 256 MCRCLLS 125MHZ 0.35UM 3.3 - Trays |
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