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參數(shù)資料
| 型號： | XCR3128XLSERIES |
| 英文描述： | 128 Macrocell CPLD |
| 中文描述： | 128個宏單元CPLD |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 91K |
| 代理商： | XCR3128XLSERIES |
DS016 (v1.8) January 8, 2002
Preliminary Product Specification
1-800-255-77781
2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm
.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
Lowest power 128 macrocell CPLD
6.0 ns pin-to-pin logic delays
System frequencies up to 145 MHz
128 macrocells with 3,000 usable gates
Available in small footprint packages
-
144-pin TQFP (108 user I/O pins)
-
144-ball CS BGA (108 user I/O)
-
100-pin VQFP (84 user I/O)
Optimized for 3.3V systems
-
Ultra low power operation
-
5V tolerant I/O pins with 3.3V core supply
-
Advanced 0.35 micron five layer metal EEPROM
process
-
Fast Zero Power (FZP) CMOS design
technology
Advanced system features
-
In-system programming
-
Input registers
-
Predictable timing model
-
Up to 23 available clocks per function block
-
Excellent pin retention during design changes
-
Full IEEE Standard 1149.1 boundary-scan (JTAG)
-
Four global clocks
-
Eight product term control terms per function block
Fast ISP programming times
Port Enable pin for additional I/O
2.7V to 3.6V supply voltage at industrial temperature
range
Programmable slew rate control per output
Security bit prevents unauthorized access
Refer to XPLA3 family data sheet (
DS012
) for
architecture description
Description
The XCR3128XL is a 3.3V 128 macrocell CPLD targeted at
power sensitive designs that require leading edge program-
mable logic solutions. A total of eight function blocks provide
3,000 usable gates. Pin-to-pin propagation delays are
6.0 ns with a maximum system frequency of 145 MHz.
TotalCMOS Design Technique for Fast
Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technol-
ogy and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate imple-
mentation allows Xilinx to offer CPLDs that are both high
performance and low power, breaking the paradigm that to
have low power, you must have low performance. Refer to
Figure 1
and
Table 1
showing the I
CC
vs. Frequency of our
XCR3128XL TotalCMOS CPLD (data taken with eight
resetable up/down, 16-bit counters at 3.3V, 25
°
C).
0
XCR3128XL 128 Macrocell CPLD
DS016 (v1.8) January 8, 2002
0
14
Preliminary Product Specification
R
Figure 1:
Typical I
CC
vs. Frequency at V
CC
= 3.3V, 25
°
C
Frequency (MHz)
DS016_01_112100
T
0
0
10
20
30
50
70
40
60
120
140
100
80
60
40
20
Table 1:
Typical I
CC
vs. Frequency at V
CC
= 3.3V, 25
°
C
Frequency (MHz)
0
1
5
10
20
40
60
80
100
120
140
Typical I
CC
(mA)
0
0.5
2.2
4.4
8.7
17.1
25.3
33.6
41.6
49.7
57.7
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