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參數(shù)資料
| 型號： | XCR3064 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | 64 Macrocell CPLD(64宏單元復雜可編程邏輯器件) |
| 中文描述： | 64宏單元CPLD（64宏單元復雜可編程邏輯器件） |
| 文件頁數(shù)： | 8/15頁 |
| 文件大?。?/td> | 124K |
| 代理商： | XCR3064 |
DC Electrical Characteristics For Commercial Grade Devices
Commercial: 0
°
C
≤
T
AMB
≤
+70
°
C; 3.0V
≤
V
CC
≤
3.6V
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
V
IL
Input voltage Low
V
CC
= 3.0V
0.8
V
V
IH
Input voltage High
V
CC
= 3.6V
2.0
V
V
I
Input clamp voltage
V
CC
= 3.0V, I
IN
= -18 mA
-1.2
V
V
OL
Output voltage Low
V
CC
= 3.0V, I
OL
= 8 mA
0.5
V
V
OH
Output voltage High
V
CC
= 3.0V, I
OH
= -8 mA
2.4
V
I
I
Input leakage current
V
IN
= 0 to V
CC
-10
10
μ
A
I
OZ
3-stated output leakage current
V
IN
= 0 to V
CC
-10
10
μ
A
I
CCQ1
Standby current
V
CC
= 3.6V, T
AMB
= 0
°
C
50
μ
A
I
CCD1, 2
Dynamic current
V
CC
= 3.6V, T
AMB
= 0
°
C at 1 MHz
1
mA
V
CC
= 3.6V, T
AMB
= 0
°
C at 50 MHz
40
mA
I
OS
Short circuit output current
3
One pin at a time for no longer than 1
second
-5
-100
mA
C
IN
Input pin capacitance
3
T
AMB
= 25
°
C, f = 1 MHz
8
pF
C
CLK
Clock input capacitance
3
T
AMB
= 25
°
C, f = 1 MHz
5
12
pF
C
I/O
I/O pin capacitance
3
T
AMB
= 25
°
C, f = 1 MHz
10
pF
Notes:
1. See
Table 1 on page 6
for typical value.
2. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs enabled
and unloaded. Inputs are tied to V
CC
or ground. This parameter guaranteed by design and characterization, not testing.
3. Typical values, not tested.
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