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參數(shù)資料
| 型號： | XCR3064 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | 64 Macrocell CPLD(64宏單元復雜可編程邏輯器件) |
| 中文描述： | 64宏單元CPLD（64宏單元復雜可編程邏輯器件） |
| 文件頁數(shù)： | 5/15頁 |
| 文件大小： | 124K |
| 代理商： | XCR3064 |
R
XCR3064: 64 Macrocell CPLD
5
www.xilinx.com
1-800-255-7778
DS036 (v1.3) October 9, 2000
This product has been discontinued. Please see
for details.Simple Timing Model
Figure 4
shows the CoolRunner Timing Model. The Cool-
Runner timing model looks very much like a 22V10 timing
model in that there are three main timing parameters,
including t
PD
, t
SU
, and t
CO
. In other CPLD architectures, the
user may be able to fit the design into the CPLD, but is not
sure whether system timing requirements can be met until
after the design has been fit into the device. This is
because the timing models of other CPLD architectures are
very complex and include such things as timing dependen-
cies on the number of parallel expanders borrowed, shar-
able expanders, varying number of X and Y routing
channels used, etc. In the XPLA architecture, the user
knows up front whether the design will meet system timing
requirements. This is due to the simplicity of the timing
model. For example, in the XCR3064 device, the user
knows up front that if a given output uses five product terms
or less, the t
PD
= 10 ns, the t
SU_PAL
= 6 ns, and the t
CO
= 7
ns. If an output is using six to 37 product terms, an addi-
tional 2.5 ns must be added to the t
PD
and t
SU
timing
parameters to account for the time to propagate through
the PLA array.
TotalCMOS Design Technique for Fast Zero
Power
Xilinx is the first to offer a TotalCMOS CPLD, both in pro-
cess technology and design technique. Xilinx employs a
cascade of CMOS gates to implement its Sum-of-Products
instead of the traditional sense amp approach. This CMOS
gate implementation allows Xilinx to offer CPLDs which are
both high performance and low power, breaking the para-
digm that to have low power, you must have low perfor-
mance. Refer to
Figure 5
and
Table 1
showing the I
CC
vs.
Frequency of our XCR3064 TotalCMOS CPLD.
Figure 4: CoolRunner Timing Model
OUTPUT PIN
INPUT PIN
SP00441
t
PD_PAL
= COMBINATORIAL PAL ONLY
t
PD_PLA
= COMBINATORIAL PAL + PLA
OUTPUT PIN
INPUT PIN
D
Q
REGISTERED
t
SU_PAL
= PAL ONLY
t
SU_PLA
= PAL + PLA
REGISTERED
t
CO
GLOBAL CLOCK PIN
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