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參數(shù)資料
| 型號： | XCR3032C |
| 廠商： | Xilinx, Inc. |
| 英文描述： | 32 Macrocell CPLD with Enhanced Clocking(帶增強時鐘控制的32宏單元復(fù)雜可編程邏輯器件) |
| 中文描述： | 32宏單元CPLD增強型時鐘（帶增強時鐘控制的32個宏單元復(fù)雜可編程邏輯器件） |
| 文件頁數(shù)： | 7/16頁 |
| 文件大小： | 313K |
| 代理商： | XCR3032C |
R
XCR3032C: 32 Macrocell CPLD with Enhanced Clocking
7
www.xilinx.com
1-800-255-7778
DS040 (v1.3) October 9, 2000
This product has been discontinued. Please see
for details.3.3V, In-System Programming (ISP)
ISP is the ability to reconfigure the logic and functionality of
a device, printed circuit board, or complete electronic sys-
tem before, during, and after its manufacture and shipment
to the end customer. ISP provides substantial benefits in
each of the following areas:
Design
-
Faster time-to-market
-
Debug partitioning and simplified prototyping
-
Printed circuit board reconfiguration during debug
-
Better device and board level testing
Manufacturing
-
Multi-Functional hardware
-
Reconfigurability for test
-
Eliminates handling of
“
fine lead-pitch
”
components
for programming
-
Reduced Inventory and manufacturing costs
-
Field Support
-
Easy remote upgrades and repair
-
Support for field configuration, re-configuration, and
customization
Improved quality and reliability
The Xilinx XCR3032C allows for 3.3V in-system program-
ming/reprogramming of its EEPROM cells via its JTAG
interface. An on-chip charge pump eliminates the need for
externally-provided supervoltages, so that the XCR3032C
may be easily programmed on the circuit board using only
the 3.3V supply required by the device for normal opera-
tion. A set of low-level ISP basic commands implemented
in the XCR3032C enable this feature. The ISP commands
implemented in the Xilinx XCR3032C are specified in
Table 5
. Please note that an ENABLE command must pre-
cede all ISP commands
unless
an ENABLE command has
already been given for a preceding ISP command.
Table 2: XCR3032C Low-Level JTAG Boundary-Scan Commands
Instruction
(Instruction Code)
Register Used
Bypass
(1111)
Bypass Register
Description
Places the 1 bit bypass register between the TDI and TDO pins, which allows the BST
data to pass synchronously through the selected device to adjacent devices during nor-
mal device operation. The Bypass instruction can be entered by holding TDI at a constant
high value and completing an Instruction-Scan cycle.
Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE
to be serially shifted out of TDO. The IDCODE instruction permits blind interrogation of
the components assembled onto a printed circuit board. Thus, in circumstances where
the component population may vary, it is possible to determine what components exist in
a product.
Idcode
(0001)
Boundary-Scan Register
Table 3: JTAG Pin Description
Pin
TCK
Name
Description
Test Clock Output
Clock pin to shift the serial data and instructions in and out of the TDI and TDO pins, re-
spectively.
Serial input pin selects the JTAG instruction mode. TMS should be driven high during user
mode operation.
Serial input pin for instructions and test data. Data is shifted in on the rising edge of TCK.
Serial output pin for instructions and test data. Data is shifted out on the falling edge of
TCK. The signal is 3-stated if data is not being shifted out of the device.
TMS
Test Mode Select
TDI
TDO
Test Data Input
Test Data Output
Table 4: XCR3032C JTAG Pinout by Package Type
Device
XCR3032C
44-pin PLCC
44-pin VQFP
(Pin Number / Macrocell #)
TMS
13/A8
7/A8
TCK
32/B8
26/B8
TDI
7/A3
1/A3
TDO
38/B3
32/B3
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| XCR3032XL-5 | XCR3032XL 32 Macrocell CPLD |
| XCR3032XL-7 | XCR3032XL 32 Macrocell CPLD |
| XCR3032XL | XCR3032XL 32 Macrocell CPLD |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCR3032C-12VQ44I | 制造商:Xilinx 功能描述: |
| XCR3032XL | 制造商:XILINX 制造商全稱:XILINX 功能描述:XCR3032XL 32 Macrocell CPLD |
| XCR3032XL-10 | 制造商:XILINX 制造商全稱:XILINX 功能描述:XCR3032XL 32 Macrocell CPLD |
| XCR3032XL-10CS48C | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 750 GATES 32 MCRCLLS 125MHZ 0.35UM 3.3 - Trays 制造商:Xilinx 功能描述:XLXXCR3032XL-10CS48C IC SYSTEM GATE |
| XCR3032XL-10CS48I | 功能描述:IC CPLD 3.3V ZERO PWR 48-CSP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:CoolRunner XPLA3 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤 |
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