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參數(shù)資料
| 型號(hào)： | XCR3032C |
| 廠商： | Xilinx, Inc. |
| 英文描述： | 32 Macrocell CPLD with Enhanced Clocking(帶增強(qiáng)時(shí)鐘控制的32宏單元復(fù)雜可編程邏輯器件) |
| 中文描述： | 32宏單元CPLD增強(qiáng)型時(shí)鐘（帶增強(qiáng)時(shí)鐘控制的32個(gè)宏單元復(fù)雜可編程邏輯器件） |
| 文件頁(yè)數(shù)： | 5/16頁(yè) |
| 文件大小： | 313K |
| 代理商： | XCR3032C |
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XCR3032C: 32 Macrocell CPLD with Enhanced Clocking
5
www.xilinx.com
1-800-255-7778
DS040 (v1.3) October 9, 2000
This product has been discontinued. Please see
for details.Simple Timing Model
Figure 4
shows the CoolRunner Timing Model. The Cool-
Runner timing model looks very much like a 22V10 timing
model in that there are three main timing parameters,
including t
PD
, t
SU
, and t
CO
. In other architectures, the user
may be able to fit the design into the CPLD, but is not sure
whether system timing requirements can be met until after
the design has been fit into the device. This is because the
timing models of competing architectures are very complex
and include such things as timing dependencies on the
number of parallel expanders borrowed, sharable expand-
ers, varying number of X and Y routing channels used, etc.
In the XPLA architecture, the user knows up front whether
the design will meet system timing requirements. This is
due to the simplicity of the timing model. For example, in
the XCR3032C device, the user knows up front that if a
given output uses five product terms or less, the t
PD
= 8 ns,
the t
SU
= 6.5 ns, and the t
CO
= 7.5 ns. If an output is using
six to 37 product terms, an additional 2.5 ns must be added
to the t
PD
and t
SU
timing parameters to account for the time
to propagate through the PLA array..
TotalCMOS Design Technique for Fast Zero
Power
Xilinx is the first to offer a TotalCMOS CPLD, both in pro-
cess technology and design technique. Xilinx employs a
cascade of CMOS gates to implement its Sum of Products
instead of the traditional sense amp approach. This CMOS
gate implementation allows Xilinx to offer CPLDs which are
both high performance and low power, breaking the para-
digm that to have low power, you must have low perfor-
mance. Refer to
Figure 5
and
Table 1
showing the I
CC
vs.
Frequency of Xilinx
’
XCR3032C TotalCMOS CPLD.
JTAG Testing Capability
JTAG is the commonly-used acronym for the Boundary
Scan Test (BST) feature defined for integrated circuits by
IEEE Standard 1149.1. This standard defines input/output
pins, logic control functions, and commands which facilitate
both board and device level testing without the use of spe-
cialized test equipment. Xilinx XCR3032C devices use the
JTAG interface for In-System Programming/Reprogram-
ming. Although only a subset of the full JTAG command set
is implemented (see
Table 2
), the devices are fully capable
of sitting in a JTAG scan chain.
The Xilinx XCR3032C's JTAG interface includes a TAP Port
defined by the IEEE 1149.1 JTAG Specification. As imple-
mented in the Xilinx XCR3032C, the TAP Port includes four
of the five pins (refer to
Table 3
) described in the JTAG
specification: TCK, TMS, TDI, and TDO. The fifth signal
defined by the JTAG specification is TRST* (Test Reset).
TRST* is considered an optional signal, since it is not actu-
ally required to perform BST or ISP. The Xilinx XCR3032C
saves an I/O pin for general purpose use by not implement-
ing the optional TRST* signal in the JTAG interface.
Instead, the Xilinx XCR3032C supports the test reset func-
tionality through the use of its power up reset circuit, which
is included in all Xilinx CPLDs. The pins associated with the
TAP Port should connect to an external pull-up resistor to
keep the JTAG pins from floating when they are not being
used (
See
“
Terminations
”
on page 8.
).
In the Xilinx XCR3032C, the four mandatory JTAG pins
each require a unique, dedicated pin on the device. The
devices come from the factory with these I/O pins set to
perform JTAG functions, but through the software, the final
function of these pins can be controlled. If the end applica-
tion will require the device to be reprogrammed at some
future time with ISP, then the pins can be left as dedicated
JTAG functions, which means they are not available for use
as general purpose I/O pins. However, unlike some
CPLDs, the Xilinx XCR3032C allow the macrocells associ-
ated with these pins to be used as buried logic when the
JTAG/ISP function is enabled. This is the default state for
the software, and no action is required to leave these pins
enabled for the JTAG/ISP functions. If, however, JTAG/ISP
is not required to leave these pins enabled for the
JTAG/ISP functions. If, however, JTAG/ISP is not required
Figure 4: CoolRunner Timing Model
OUTPUT PIN
INPUT PIN
SP00552
t
PD_PAL
= COMBINATORIAL PAL ONLY
t
PD_PLA
= COMBINATORIAL PAL + PLA
OUTPUT PIN
INPUT PIN
D
Q
REGISTERED
t
SU_PAL
= PAL ONLY
t
SU_PLA
= PAL + PLA
REGISTERED
t
CO
GLOBAL CLOCK
PIN
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCR3032XL-10 | XCR3032XL 32 Macrocell CPLD |
| XCR3032XL-5 | XCR3032XL 32 Macrocell CPLD |
| XCR3032XL-7 | XCR3032XL 32 Macrocell CPLD |
| XCR3032XL | XCR3032XL 32 Macrocell CPLD |
| XCR3032 | 32 Macrocell CPLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCR3032C-12VQ44I | 制造商:Xilinx 功能描述: |
| XCR3032XL | 制造商:XILINX 制造商全稱:XILINX 功能描述:XCR3032XL 32 Macrocell CPLD |
| XCR3032XL-10 | 制造商:XILINX 制造商全稱:XILINX 功能描述:XCR3032XL 32 Macrocell CPLD |
| XCR3032XL-10CS48C | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 750 GATES 32 MCRCLLS 125MHZ 0.35UM 3.3 - Trays 制造商:Xilinx 功能描述:XLXXCR3032XL-10CS48C IC SYSTEM GATE |
| XCR3032XL-10CS48I | 功能描述:IC CPLD 3.3V ZERO PWR 48-CSP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:CoolRunner XPLA3 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤(pán) |
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