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參數(shù)資料
| 型號(hào)： | XCR3032C |
| 廠商： | Xilinx, Inc. |
| 英文描述： | 32 Macrocell CPLD with Enhanced Clocking(帶增強(qiáng)時(shí)鐘控制的32宏單元復(fù)雜可編程邏輯器件) |
| 中文描述： | 32宏單元CPLD增強(qiáng)型時(shí)鐘（帶增強(qiáng)時(shí)鐘控制的32個(gè)宏單元復(fù)雜可編程邏輯器件） |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大?。?/td> | 313K |
| 代理商： | XCR3032C |
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R
XCR3032C: 32 Macrocell CPLD with Enhanced Clocking
DS040 (v1.3) October 9, 2000
www.xilinx.com
1-800-255-7778
4
This product has been discontinued. Please see
for details.Macrocell Architecture
Figure 3
shows the architecture of the macrocell used in
the CoolRunner XCR3032C. The macrocell can be config-
ured as either a D- or T-type flip-flop or a combinatorial
logic function. A D-type flip-flop is generally more useful for
implementing state machines and data buffering while a
T-type flip-flop is generally more useful in implementing
counters. Each of these flip-flops can be clocked from any
one of four sources. Two of the clock sources (CLK0 and
CLK1) are connected to low-skew, device-wide clock net-
works designed to preserve the integrity of the clock signal
by reducing skew between rising and falling edges. Clock 0
(CLK0) is designated as a
“
synchronous
”
clock and must
be driven by an external source. Clock 1 (CLK1) can be
used as a
“
synchronous
”
clock that is driven by an external
source, or as an
“
asynchronous
”
clock that is driven by a
macrocell equation. Both CLK0 and CLK1 can clock the
macrocell flip-flops on either the rising edge or the falling
edge of the clock signal. The other clock sources are two of
the six control terms (CT2 and CT3) provided in each logic
block. These clocks can be individually configured as either
a PRODUCT term or SUM term equation created from the
36 signals available inside the logic block. The timing for
asynchronous and control term clocks is different in that the
Tco time is extended by the amount of time that it takes for
the signal to propagate through the array and reach the
clock network, and the Tsu time is reduced.
The six control terms of each logic block are used to control
the asynchronous Preset/Reset of the flip-flops and the
enable/disable of the output buffers in each macrocell.
Control terms CT0 and CT1 are used to control the asyn-
chronous Preset/Reset of the macrocell's flip-flop. Note
that the Power-on Reset leaves all macrocells in the
“
zero
”
state when power is properly applied, and that the Pre-
set/Reset feature for each macrocell can also be disabled.
Control terms CT2 and CT3 can be used as a clock signal
to the flip-flops of the macrocells, and as the Output Enable
of the macrocell's output buffer. Control terms CT4 and
CT5 can be used to control the Output Enable of the mac-
rocell's output buffer. Having four dedicated Output Enable
control terms ensures that the CoolRunner
devices are
PCI compliant. The output buffers can also be always
enabled or always disabled. All CoolRunner
devices also
provide a Global 3-state (GTS) pin, which, when enabled
and pulled Low, will 3-state all the outputs of the device.
This pin is provided to support
“
In-Circuit Testing
”
or
“
Bed-of-Nails
”
testing.
There are two feedback paths to the ZIA: one from the
macrocell, and one from the I/O pin. The ZIA feedback path
before the output buffer is the macrocell feedback path,
while the ZIA feedback path after the output buffer is the I/O
pin feedback path. When the macrocell is used as an out-
put, the output buffer is enabled, and the macrocell feed-
back path can be used to feedback the logic implemented
in the macrocell. When the I/O pin is used as an input, the
output buffer will be 3-stated and the input signal will be fed
into the ZIA via the I/O feedback path, and the logic imple-
mented in the buried macrocell can be fed back to the ZIA
via the macrocell feedback path. It should be noted that
unused inputs or I/Os should be properly terminated (See
the section on
“
Terminations
”
on page 8
in this data sheet
and the app note
Terminating Unused I/O Pins in Xilinx
CoolRunner XPLA1 and XPLA2 CPLDs.
).
Figure 3: XCR3032C Macrocell Architecture
(INIT
D/T
Q
SP00551
CLK0
PAL
PLA
CLK0
CLK1
CLK1
TO ZIA
GND
CT0
GTS
C
C
C
C
V
G
C
GND
相關(guān)PDF資料 |
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|---|---|
| XCR3032XL-10 | XCR3032XL 32 Macrocell CPLD |
| XCR3032XL-5 | XCR3032XL 32 Macrocell CPLD |
| XCR3032XL-7 | XCR3032XL 32 Macrocell CPLD |
| XCR3032XL | XCR3032XL 32 Macrocell CPLD |
| XCR3032 | 32 Macrocell CPLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCR3032C-12VQ44I | 制造商:Xilinx 功能描述: |
| XCR3032XL | 制造商:XILINX 制造商全稱:XILINX 功能描述:XCR3032XL 32 Macrocell CPLD |
| XCR3032XL-10 | 制造商:XILINX 制造商全稱:XILINX 功能描述:XCR3032XL 32 Macrocell CPLD |
| XCR3032XL-10CS48C | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 750 GATES 32 MCRCLLS 125MHZ 0.35UM 3.3 - Trays 制造商:Xilinx 功能描述:XLXXCR3032XL-10CS48C IC SYSTEM GATE |
| XCR3032XL-10CS48I | 功能描述:IC CPLD 3.3V ZERO PWR 48-CSP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:CoolRunner XPLA3 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤 |
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