R
Although
Table 10
lists configuration signals for only one,
two, four, or eight Slave-Serial chain systems, any number
of Slave-Serial chains from one to eight are supported in the
System ACE software. The System ACE software assigns
the data streams for each Slave-Serial chain starting from
CFG_DATA[0] up to CFG_DATA[N-1] where N is the number
of Slave-Serial chains in the system.
Slave-SelectMAP/Slave-Parallel
The System ACE MPM conveniently supports high-speed,
sequential configuration of up to four Xilinx FPGAs via the
8-bit-wide SelectMAP configuration bus or four Spartan-II
devices via the 8-bit-wide Slave-Parallel bus. The System
ACE MPM generates a maximum configuration clock rate of
19 MHz. The maximum bit delivery rate is 152 Mb/s. (152
Mb/s is the maximum read rate from the AMD Flash mem-
ory in the System ACE MPM.)
The connectivity between the System ACE MPM and the
FPGAs on the SelectMAP bus is similar to the connectivity
between a Xilinx PROM and a Slave-SelectMAP FPGA with
the addition of the CFG_WRITE and separate CFG_CS
(chip select) signals. All configuration signals from the Sys-
tem ACE MPM are common to all of the target FPGAs on
the SelectMAP bus, except that the CS_B signal of the first
FPGA must be connected to the System ACE MPM
CFG_CS[0] pin, and the CS_B signal of the second FPGA
must be connected to the System ACE MPM CFG_CS[1]
pin, etc. See
Figure 8
for a schematic diagram of the
Slave-SelectMAP configuration connections, and
Table 11
for a list of the Slave-SelectMAP connections for up to four
target FPGAs.
The Spartan-II Slave-Parallel mode has the same structure
and protocol as the Slave-SelectMAP mode. Therefore, the
Slave-SelectMAP figure and table apply to the Spartan-II
Slave-Parallel mode with the appropriate signal name trans-
lations noted in
Table 11
System ACE MPM
Single
Slave-Serial Chain
Two
Slave-Serial Chains
Four
Slave-Serial Chains
Eight
Slave-Serial Chains
CFG_DATA[4]
DIN on first FPGA of
Chain 4
CFG_DATA[5]
DIN on first FPGA of
Chain 5
CFG_DATA[6]
DIN on first FPGA of
Chain 6
CFG_DATA[7]
DIN on first FPGA of
Chain 7
Table 10:
Slave-Serial FPGA Configuration Signals
(Continued)