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參數(shù)資料
| 型號(hào)： | XC9572 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | In-System Programmable CPLD(在系統(tǒng)復(fù)雜可編程邏輯器件) |
| 中文描述： | 在系統(tǒng)可編程的CPLD（在系統(tǒng)復(fù)雜可編程邏輯器件） |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 41K |
| 代理商： | XC9572 |
XAPP070 July, 1997 (Version 1.1)
1-13
1
In-System Programming
Using the Xilinx Download Cables
The EZTag software can be used with either the Xilinx
JTAG parallel download cable or the Xilinx serial XChecker
cable.
IBM PC compatible systems can use the Xilinx high speed
Parallel Cable III (part number DLC5). The cable pod
includes port protection and drive circuitry which requires a
5V power supply that is usually is supplied by the target
system. This cable operates TCK at a frequency of
between 100KHz and 300Khz which is determined by the
port speed of the host computer.
Sun and HP workstations (as well as IBM PC-compatible
systems) use the Xilinx XChecker cable, which connects to
the computer’s serial port. The XChecker cable pod con-
tains an XC3042 FPGA and 1Mbit of static RAM. The
FPGA is configured to operate as a UART to facilitate host-
cable communications. It also includes circuitry to enable
high speed 1149.1 TAP signal processing the collecting
TDO results in XChecker’s static RAM. The TDO data can
then be uploaded to the host. Like the parallel cable, the
XChecker cable requires 5V to operate and this is usually
provided by the target system.
When addressing the TAP the XChecker cable operates at
TCK frequencies of approximately 1 MHz, which is con-
trolled by a crystal in the XChecker cable pod. Although the
cable TAP driver can operate at 1MHz, the overall speed of
this cable is determined by the serial port throughput which
is typically 38K baud.
The parallel and serial cable characteristics are:
Power - A 5V power supply capable of providing 125
mA peak current and 60 mA steady state is required.
The parallel cable requires a 5V power supply capable
of providing 20 mA current.
Drive Capabilities - The XChecker cable outputs are
capable of sourcing or sinking up to 4 mA. The parallel
cable outputs are capable of sourcing or sinking up to
20 mA.
Special considerations - For both the XChecker and
parallel download cables, the 1149.1 TAP drive
electronics is in the cable pod. This should be taken into
account when extending the signal reach from the pod
to the system. When extending the cable from the port
connection side, the drive capabilities of the host
computer’s port itself must be considered.
Concurrent Program and Erase Modes
One operating mode of the EZTag software performs con-
current erasing and programming. The advantage of this
approach is speed; the overall programming time is dic-
tated by the slowest part in the boundary-scan chain. Also,
the total number of vectors required is optimized. The dis-
advantage of this approach is that the system must supply
a peak operating current equal to that required by all parts
being programmed or erased concurrently. For more infor-
mation on how to use this feature in EZTag, please see the
Xilinx EZTag User’s Guide
Note
: although XC9500 parts can be programmed concur-
rently, the current EZTag software does not generate an
SVF file that supports this operation. The current EZTag
generates an SVF file that bypasses all parts except the
one being programmed.
ISP Mode I/O Behavior
The functional pins of the device transition to a high-imped-
ance state when ISP mode is entered using the ISPEN
instruction. At the completion of an ISP programming or
erase operation, the ISPEX instruction is executed. When
leaving ISPEX mode (by shifting in an new boundary-scan
instruction other than ISPEN), the device initializes to its
programmed state; the functional pins take on their
selected operations (input, output, or bidirectional) and the
device registers take on their pre-selected initial values.
System-Level Design Issues
The normal operating mode of a system or a device in the
system is known as mission mode which is different from
test mode. When operating a device in boundary-scan test
mode (such as when using either INTEST or EXTEST) as
well as when performing ISP operations, the device is
effectively disconnected from the overall system. When the
operation is completed, the device is re-connected to the
system. This can sometimes result in unpredictable system
behavior. Additional discussion regarding this problem can
be found in “The Boundary-Scan Handbook” by Ken
Parker. Fortunately, the XC9500 family supplies two propri-
etary boundary-scan instructions that serve to alleviate this
problem.
XC9500 Mission Mode Exit and Re-Entry
Techniques
The XC9500 devices support two boundary-scan instruc-
tions that can be used to help alleviate the problems asso-
ciated with exiting and re-entering mission mode. The
instructions are ISPEN (ISP enable) and ISPEX (ISP exit).
ISPEN
- The ISPEN instruction is used at the beginning
of every block of ISP operations that will attempt to
access for alteration or read the device internal program
memory (such as program, erase, verify, etc.). When
the device is in ISPEN mode, the device I/O pins
immediately enter a state in which they are floating with
a weak pull-up resistor enabled on each pin. The device
pins therefore neither drive nor sense external signal
levels.
ISPEX
- The ISPEX instruction is used to conclude
every block of ISP operations that have either been
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| XC9572-10PC44 | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC9572 In-System Programmable CPLD |
| XC957210PC44C | 制造商:Xilinx 功能描述: |
| XC9572-10PC44C | 功能描述:IC CPLD 72 MCELL C-TEMP 44-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:XC9500 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤 |
| XC9572-10PC44C0166 | 制造商:Xilinx 功能描述: |
| XC9572-10PC44I | 功能描述:IC CPLD 72 MCELL I-TEMP 44-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:XC9500 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤 |
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