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| 型號(hào)： | XC9572 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | In-System Programmable CPLD(在系統(tǒng)復(fù)雜可編程邏輯器件) |
| 中文描述： | 在系統(tǒng)可編程的CPLD（在系統(tǒng)復(fù)雜可編程邏輯器件） |
| 文件頁(yè)數(shù)： | 2/6頁(yè) |
| 文件大小： | 41K |
| 代理商： | XC9572 |
Using In-System Programmability in Boundary-Scan Systems
1-10
XAPP070 July, 1997 (Version 1.1)
TAP AC Parameters
Table 1
shows the timing parameters for the TAP wave-
forms shown in
Figure 1
.
Terminating TAP pins
The XC9500 TDI and TMS pins have internal 15Kohm pull-
up resistors, which are required by the 1149.1 standard.
Because these pins are internally terminated, no further
termination is required on the TAP connections.
Capacitive Decoupling
Decouple the Vcc input with a 0.1 uF capacitor connected
to the nearest ground plane (low inductance surface mount
capacitors are recommended). Decouple the printed circuit
board power inputs with 0.1 uF ceramic and 100 uF electro-
lytic capacitors. This helps to provide a stable, noise free
power supply to the ISP parts.
Free Running Oscillators
Boundary-scan operations often involve the transmission of
long streams of data through long and complex paths that
traverse the entire system. Often, the presence of active
clocks and free running oscillators will couple noise onto
the boundary-scan chain TAP signals. To increase the reli-
ability of boundary-scan and ISP operations, equip your
system with a clock and oscillator disable. The disable
should be activated for all test and program operations
when using the download cable, ATE or third party sys-
tems.
Calculating Maximal Chain Lengths
The XC9500 TAP pins have approximately 5 pF of signal
loading. Because each TDI input is driven by only one TDO
output (or equivalent single drive) there are no signal limita-
tions related to those connections beyond those of stan-
dard board interconnect design rules.
The maximum TDO frequency will be 1/2 of the maximum
TCK frequency. Because TCK and TMS are parallel driven
signals the maximum number of parts in a single boundary-
scan chain is determined by the ability of the TCK and TMS
drivers to deliver the signals at the appropriate frequencies
to the parts in the boundary-scan chain. Standard board-
layout design rules also apply here.
If the boundary-scan chain includes more than 6 devices,
buffered distribution of TMS and TCK are recommended.
Part Enable Ordering
The ISPEX instruction allows the flexibility to enable parts
in an arbitrary order. In some systems the order in which
parts are enabled is critical. For instance, if a slave device
awakens before its controller, it may enter an error condi-
tion from which it cannot exit.
The EZTag software enables each part immediately after
programming. In concurrent mode the parts are enabled in
order from system TDI to system TDO.
Creating Boundary-Scan Chains
There are a number of possibilities for creating boundary
scan chains, several of which are discussed in the following
sections
Single Port Serial Chain
The most simple and widely-used boundary-scan configu-
ration is the single port serial chain shown in
Figure 2
, and
only this type of configuration is supported by the EZTag
software. In this configuration, four pins are allocated in the
system to facilitate connection of the TCK (clock), TMS
(mode), TDI (Test Data Input), and TDO (Test Data Output)
signals.
All devices in the chain share the TCK and TMS signals.
The system TDI signal is connected to the TDI input of the
first device in the boundary-scan chain. The TDO signal
from that first device is connected to the TDI input of the
second device in the chain and so on. The last device in the
chain has its TDO output connected to the system TDO pin.
Other more complex chain variations are discussed later in
this application note. Software supplied by third party
developers supports these complex chain configurations.
Table 1: Test Access Port Timing Parameters (ns)
Symbol
TCKMIN
TMSS
TMSH
TDIS
TDIH
TDOZX
TDOXZ
TDOV
TINS
TINH
TIOV
Parameter
Min
100
10
10
15
25
Max
TCK Minimum Clock Period
TMS Setup Time
TMS Hold Time
TDI Setup Time
TDI Hold Time
TDO Float to Valid Delay
TDI Valid to Float Delay
TDO Valid Delay
I/O Setup Time
I/O Hold Time
EXTEST Output Valid Delay
35
35
35
15
30
55
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| XC9572-10PC44 | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC9572 In-System Programmable CPLD |
| XC957210PC44C | 制造商:Xilinx 功能描述: |
| XC9572-10PC44C | 功能描述:IC CPLD 72 MCELL C-TEMP 44-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:XC9500 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門(mén)數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤(pán) |
| XC9572-10PC44C0166 | 制造商:Xilinx 功能描述: |
| XC9572-10PC44I | 功能描述:IC CPLD 72 MCELL I-TEMP 44-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:XC9500 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門(mén)數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤(pán) |
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