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參數(shù)資料
| 型號： | XC95216 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | In-System Programmable CPLD(在系統(tǒng)復(fù)雜可編程邏輯器件) |
| 中文描述： | 在系統(tǒng)可編程的CPLD（在系統(tǒng)復(fù)雜可編程邏輯器件） |
| 文件頁數(shù)： | 4/5頁 |
| 文件大小： | 81K |
| 代理商： | XC95216 |
XC9500 Remote Field Upgrade
4
XAPP 102 January 13, 1998 (Version 1.0)
ing states, HIGH and LOW, keep the XSVF data bus, and
processor data bus in high impedance.
In the VHDL design, the top level connectivity file (IRDNLD)
logically connects the VHDL design using named-order
association. The state bits for the UART, and timing inter-
face control engine are defined in a package called
"datatype". See the comments in the VHDL code.
Programming In-System XC9500
CPLDs via a Remote Source
Serial Vector Format (SVF) is a syntax specification for
describing high level IEEE 1149.1 (JTAG) bus operations.
Xilinx Serial Vector Format (XSVF) is a compressed, binary
version of the SVF file designed specifically for embedded
applications. XC9500 CPLDs use the IEEE 1149.1 Bound-
ary Scan Standard for in-system programming (ISP). Appli-
cation note XAPP058 describes how to create both the
SVF, and XSVF file. This application note extends the
XSVF file with a Perl script to calculate the number of XSVF
file bytes . Once the binary XSVF file is complete with num-
ber of bytes, the reader should use the binary to Intel Hex
translator in Appendix D (XAPP058) to create an Intel Hex
file suitable for embedded applications. The Intel Hex con-
verted XSVF file is then transferred remotely to the embed-
ded application described herein, and thereby upgrades an
in-system XC9500 CPLD. The remote system should use a
simple UART, coupled with the Siemens Infrared Data
Transceiver to transfer the XSVF file.
Additional Hardware Details
As shown in
Figure 1
, this design requires only an 8051
microcontroller, address latch, XC9500 CPLD to decode
and upgrade the XSVF RAM, and enough EPROM or non-
volatile memory to contain the embedded C code detailed
in application note, XAPP058.
The VHDL allows the XC95108 CPLD to operate in the
background, receiving infrared data and updating the XSVF
RAM, while the embedded processor works in the fore-
ground on other bus operations. In
Figure 1
, the 8051 mul-
tiplexes it's port 0 for both data and address bus operations.
The ALE signal causes the 74x373 to latch the lower order
address, and the higher order address is output on port 2.
The 8051's port 0 then floats, allowing the selected mem-
ory to drive the data inputs. The !PSEN signal goes low to
activate an 8051 program read operation from the EPROM,
or the SEL_RAM signal from the XC95108 CPLD goes
“l(fā)ow” to activate a memory read from the scratch pad RAM.
The EPROM contains the embedded C code detailed in
XAPP058. The clock is a TTL type crystal rated at 16MHz
which provides global clocking in the XC95108, and the
8051 microcontroller. The 16MHz crystal is also 16 times
the infrared data transfer rate.
Modifying the Design
This application note can be used as-is to reconfigure any
in-system XC9500 CPLD. If your system contains multiple
CPLDs, or you are doing more then the typical ERASE/
PROGRAM operations (i.e. ERASE/PROGRAM/VERIFY,
or BYPASS), you may need to modify the VHDL code to
include 4 bytes for the "length_count", and replace the
existing XSVF RAM with a larger one. Check the size of the
XSVF file generated by the M1 JTAG Programmer first. If
the file is larger than 65,536 bytes, you will need to modify
the VHDL code as described above. Also, you must modify
the XSVF sizing utility (Perl script) with the following:
$ss=pack("I", $size);
The original code contains an "S" to signify SHORT INTE-
GER. Replacing the "S" with an "I" yields a 4 byte integer.
Finally, add one address line to the VHDL code. In other
words,
XSVF_ADD: standard_logic_vector(15 downto 0).
Planning for Field Upgrade
One additional address line may or may not cause prob-
lems. If the designer didn't leave room for growth and
packed the design to 100%, the additional address line can
cause problems. Some designers weigh cost and leaving
room for growth as two separate entities. Printed circuit
rework can be costly, and typically results from a hasty
design change that expands the design.
Pin-locking refers to allowing the CPLD software to fit a
design based on an algorithm that tends to spread equa-
tions throughout the CPLD. Once the design is fit, future
design changes can be made without compromising the
original pin-out. The XC9500 CPLD has a very robust pin-
locking architecture, designed for ISP However, it's still
important to recognize that if a design is likely to grow, it's
best not to force the software to override the pin-locking
algorithm, and pack the design. Some techniques key to
leaving room for growth are:
1. Don't pack a design more than 85%.
Figure 4
below
shows a partial summary of the fitting results for the
VHDL code in this application note
Notice that the Macrocells Used is 79%, or 86 out of
108. Also notice that out of 69 total user I/O, 9 are left
over. This leaves a cushion for future changes.
2. Provide traces on your circuit board that physically con-
nect I/O to future applications. If it doesn't alter the oper-
ation, tie the trace to a known logic level. Xilinx
recommends not using unused I/O to board ground, and
use the "Create Programmable Grounds" option in the
Xilinx CPLD Software.
3. If specific I/O pins need to be reserved, provide
“dummy” functions such as:
OUT = IN
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| XC9521610HQ208C | 制造商:xilinx 功能描述:* |
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| XC95216-10HQ208C0586 | 制造商:Xilinx 功能描述: |
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