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參數(shù)資料
| 型號： | XC95216 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | In-System Programmable CPLD(在系統(tǒng)復(fù)雜可編程邏輯器件) |
| 中文描述： | 在系統(tǒng)可編程的CPLD（在系統(tǒng)復(fù)雜可編程邏輯器件） |
| 文件頁數(shù)： | 2/5頁 |
| 文件大小： | 81K |
| 代理商： | XC95216 |
XC9500 Remote Field Upgrade
2
XAPP 102 January 13, 1998 (Version 1.0)
embedded microcontroller, indicating that the updated
XSVF data is ready in XSVF RAM. The microcontroller will
drive the data down the JTAG port which is attached to the
ISP parts to be upgraded. In
Figure 1
, the EPROM holds
the 8051 code which performs the embedded download
operation detailed in XAPP058.
Figure 1: Block Diagram
UART Design
The UART design contains 4 states: MARK, DATA,
STOP_BIT, and ERR, and is designed to parse the XSVF
file, stripping out the start and stop bits, while registering
the 8 data bits. The MARK state is essentially the rest state
once the XSVF data transfer is complete, but also serves to
verify the start bit in an RS232 data sequence. A start bit is
verified by 8 counts while input IR_IN is "low". Once the
start bit is verified, the state machine moves to the DATA
state. A data bit is registered into an 8 bit register contain-
ing an "offset" that is incremented by one each time a bit is
registered. Data bits are registered after 16 counts. Once
the 8 data bits are registered, the state machine moves to
the STOP_BIT state. In the STOP_BIT state, the counter
counts to 16 and verifies that IR_IN is "low". If IR_IN is
"low", the state machine will advance to the MARK state
when IR_IN transitions to a "high". If IR_IN is "high" after 16
counts, the state machine will enter the ERR state to signal
that a transmit error has occurred. While in the STOP_BIT
state, the UART flags the timing interface control engine to
indicate that data is ready to be written into XSVF RAM.
Timing Interface Control Engine
The timing interface control engine is the heart of the
remote field upgrade design. It contains 4 states: HIGH,
LOW, DOWNLOAD, and ISP The first two bytes of the
XSVF file represent the number of XSVF file bytes to be
transferred. States HIGH, and LOW, register the high, and
low bytes, respectively, into signal "length_count". While in
the DOWNLOAD state, the "length_count" is decremented
each time a byte is written into XSVF RAM. The timing
interface control engine also increments the internal
address counter, "add_cntr", and controls the "write" signal
allowing data to be written into XSVF RAM. Once the entire
XSVF file has been written into XSVF RAM, the timing
interface control engine enters the ISP state. The ISP state
interrupts the embedded processor, which eventually vec-
tors off to it's interrupt service routine to reconfigure an in-
XC95108
8
AD0-7
L
A
2
AD0-7
AD8-15
RAM
Scratch
RAM
XSVF
clock
control
P0
P2
P1
EPROM
Latch
μ
controller
JTAG
Port
3
select
Infrared
Data In
AD07
DATA
ADDR
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| XC95216-10BG352I | 功能描述:IC CPLD 216 MCELL I-TEMP 352-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:XC9500 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤 |
| XC9521610HQ208C | 制造商:xilinx 功能描述:* |
| XC95216-10HQ208C | 功能描述:IC CPLD 216 MCELL C-TEMP 208HQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:XC9500 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤 |
| XC95216-10HQ208C0586 | 制造商:Xilinx 功能描述: |
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