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參數資料
| 型號： | XC9500 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | XC9500 In-System Programmable CPLD Family |
| 中文描述： | XC9500在系統可編程CPLD系列 |
| 文件頁數： | 5/16頁 |
| 文件大小： | 172K |
| 代理商： | XC9500 |
XC9500 In-System Programmable CPLD Family
DS063 (v5.1) September 22, 2003
Product Specification
www.xilinx.com
1-800-255-7778
5
R
All global control signals are available to each individual
macrocell, including clock, set/reset, and output enable sig-
nals. As shown in
Figure 4
, the macrocell register clock
originates from either of three global clocks or a product
term clock. Both true and complement polarities of a GCK
pin can be used within the device. A GSR input is also pro-
vided to allow user registers to be set to a user-defined
state.
Figure 4:
Macrocell Clock and Set/Reset Capability
D/T
S
R
Macrocell
DS063_04_110501
I/O/GSR
Product Term Set
Product Term Clock
Product Term Reset
Global Set/Reset
Global Clock 1
Global Clock 2
Global Clock 3
I/O/GCK3
I/O/GCK2
I/O/GCK1
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